AD9985SLASHPCB datasheet(24/32 Pages) AD

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AD9985

Rev. 0 | Page 24 of 32

Table 33. Detected Hsync Input Polarity Status

Hsync Polarity

Status

Result

Negative

Positive

Vsync Detect

This bit is used to indicate when activity is detected on

the Vsync input pin (Pin 31). If Vsync is held steady

high or low, activity will not be detected.

Table 34. Vsync Detection Results

Detect

Function

No Activity Detected

Activity Detected

The Sync Processing Block Diagram (Figure 14) shows

where this function is implemented.

AVS – Active Vsync

This bit indicates which Vsync source is being used:

the Vsync input or output from the sync separator.

Bit 4 in this register determines which is active. If both

Vsync and SOG are detected, the user can determine

which has priority via Bit 0 in Register 0EH. The user

can override this function via Bit 1 in Register 0EH. If

the override bit is set to Logic 1, this bit will be forced

to whatever the state of Bit 0 in Register 0EH is set to.

Table 35. Active Vsync Results

Bit 4, Reg 14H

Bit 1, Reg 0EH

(Vsync Detect)

(Override)

AVS

Bit 0 in 0EH

AVS = 0 means Vsync input.

AVS = 1 means Sync separator.

The override bit is in Register 0EH, Bit 1.

Detected Vsync Output Polarity Status

This bit reports the status of the Vsync output polarity

detection circuit. It can be used to determine the

polarity of the Vsync output. The detection circuit’s

location is shown in the Sync Processing Block

Diagram (Figure 14).

Table 36. Detected Vsync Output Polarity Status

Vsync Polarity Status

Result

Active Low

Active High

Sync-on-Green Detect

This bit is used to indicate when sync activity is

detected on the Sync-on-Green input pin (Pin 49).

Table 37. Sync-on-Green Detection Results

Detect

Function

No Activity Detected

Activity Detected

The Sync Processing Block Diagram (Figure 14) shows

where this function is implemented.

Detected Coast Polarity Status

This bit reports the status of the Coast input polarity

detection circuit. It can be used to determine the

polarity of the Coast input. The detection circuit’s

location is shown in the Sync Processing Block

Diagram (Figure 14).

Table 38. Detected Coast Input Polarity Status

Polarity Status

Result

Coast Polarity Negative

Coast Polarity Positive

This indicates that Bit 1 of Register 5 is the 4:2:2

output mode select bit.

4:2:2 Output Mode Select

This bit configures the output data in 4:2:2 mode. This

mode can be used to reduce the number of data lines

used from 24 down to 16 for applications using YUV,

YCbCr, or YPbPr graphics signals. A timing diagram

for this mode is shown in Figure 11.

Recommended input and output configurations are

shown in Table 39.

Table 39. 4:2:2 Output Mode Select

Select

Output Mode

4:2:2

4:4:4

Table 40. 4:2:2 Input/Output Configuration

Input

Channel

Connection

Output Format

Red

U/V

Green

Blue

High Impedance

7:0

Red Target Code

This specifies the targeted value of the final offset for

the Red channel when auto offset is employed

(Register 0x1D Bit 7 = 1). Default is 4.

7:0

Green Target Code

This specifies the targeted value of the final offset for

the Green channel when auto offset is employed

(Register 0x1D Bit 7 = 1). Default is 4.

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