| Electronic Components Datasheet Search |
|
AT89C5131-RDTIL Datasheet(PDF) 115 Page - ATMEL Corporation |
|
|
|||||||||||||||||||||||||||||
AT89C5131-RDTIL Datasheet(HTML) 115 Page - ATMEL Corporation |
|
115 / 176 page ![]() 115 AT89C5131 4136B–USB–09/03 USB Device Firmware Upgrade (DFU) The USB Device Firmware Update (DFU) protocol can be used to upgrade the on-chip Flash memory of the AT89C5131. This allows the implementation of product enhance- ments and patches to devices that are already in the field. Two different configurations and descriptor sets are used to support DFU functions. The Run-Time configuration co- exists with the usual functions of the device, which may be USB Mass Storage for the AT89C5131. It is used to initiate DFU from the normal operating mode. The DFU config- uration is used to perform the firmware update after device re-configuration and USB reset. It excludes any other function. Only the default control pipe (endpoint 0) is used to support DFU services in both configurations. The only possible value for the wMaxPacketSize in the DFU configuration is 32 bytes, which is the size of the FIFO implemented for endpoint 0. Description The USB device controller provides the hardware that the AT89C5131 needs to inter- face a USB link to a data flow stored in a double port memory (DPRAM). The USB controller requires a 48 MHz ±0.25% reference clock, which is the output of the AT89C5131 PLL (see Section “PLL”, page 20) divided by a clock prescaler. This clock is used to generate a 12 MHz Full-speed bit clock from the received USB differen- tial data and to transmit data according to full speed USB device tolerance. Clock recovery is done by a Digital Phase Locked Loop (DPLL) block, which is compliant with the jitter specification of the USB bus. The Serial Interface Engine (SIE) block performs NRZI encoding and decoding, bit stuff- ing, CRC generation and checking, and the serial-parallel data conversion. The Universal Function Interface (UFI) realizes the interface between the data flow and the Dual Port RAM. Figure 53. USB Device Controller Block Diagram SIE DPLL USB D+/D- Buffer UFI 12 MHz 48 MHz +/- 0.25% D+ Up to 48 MHz UC_sysclk C51 Microcontroller Interface D- |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |