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AT89C5131-RDTIL Datasheet(PDF) 21 Page - ATMEL Corporation |
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AT89C5131-RDTIL Datasheet(HTML) 21 Page - ATMEL Corporation |
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21 / 176 page  21 AT89C5131 4136B–USB–09/03 PLL Programming The PLL is programmed using the flow shown in Figure 9. As soon as clock generation is enabled user must wait until the lock indicator is set to ensure the clock output is stable. Figure 9. PLL Programming Flow Divider Values To generate a 48 MHz clock using the PLL, the divider values have to be configured fol- lowing the oscillator frequency. The typical divider values are shown in Table 27. Table 27. Typical Divider Values PLL Programming Configure Dividers N3:0 = xxxxb R3:0 = xxxxb Enable PLL PLLEN = 1 PLL Locked? LOCK = 1? Oscillator Frequency R+1 N+1 PLLDIV 3 MHz 16 1 F0h 6 MHz 8 1 70h 8 MHz 6 1 50h 12 MHz 4 1 30h 16 MHz 3 1 20h 18 MHz 8 3 72h 20 MHz 12 5 B4h 24 MHz 2 1 10h 32 MHz 3 2 21h 40 MHz 12 10 B9h |
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