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AT89C5131-RDTIL Datasheet(PDF) 143 Page - ATMEL Corporation |
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AT89C5131-RDTIL Datasheet(HTML) 143 Page - ATMEL Corporation |
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143 / 176 page  143 AT89C5131 4136B–USB–09/03 Table 101. UEPINT Register UEPINT (S:F8h read-only) USB Endpoint Interrupt Register Reset Value = 00h 765 43210 - EP6INT EP5INT EP4INT EP3INT EP2INT EP1INT EP0INT Bit Number Bit Mnemonic Description 7- Reserved The value read from this bit is always 0. Do not set this bit. 6EP6INT Endpoint 6 Interrupt This bit is set by hardware when an interrupt is triggered by the (see Table 96 on page 139) and this endpoint interrupt is enabled by the UEPIEN Register UEPIEN (S:C2h) USB Endpoint Interrupt Enable Register (see Figure 102 on page 144). This bit is cleared by software. 5EP5INT Endpoint 5 Interrupt This bit is set by hardware when an interrupt is triggered by the (see Table 96 on page 139) and this endpoint interrupt is enabled by the UEPIEN Register UEPIEN (S:C2h) USB Endpoint Interrupt Enable Register (see Figure 102 on page 144). This bit is cleared by software. 4EP4INT Endpoint 4 Interrupt This bit is set by hardware when an interrupt is triggered by the (see Table 96 on page 139) and this endpoint interrupt is enabled by the UEPIEN Register UEPIEN (S:C2h) USB Endpoint Interrupt Enable Register (see Figure 102 on page 144). This bit is cleared by software. 3EP3INT Endpoint 3 Interrupt This bit is set by hardware when an interrupt is triggered by the (see Table 96 on page 139) and this endpoint interrupt is enabled by the UEPIEN Register UEPIEN (S:C2h) USB Endpoint Interrupt Enable Register (see Figure 102 on page 144). This bit is cleared by software. 2EP2INT Endpoint 2 Interrupt This bit is set by hardware when an interrupt is triggered by the (see Table 96 on page 139) and this endpoint interrupt is enabled by the UEPIEN Register UEPIEN (S:C2h) USB Endpoint Interrupt Enable Register (see Figure 102 on page 144). This bit is cleared by software. 1EP1INT Endpoint 1 Interrupt This bit is set by hardware when an interrupt is triggered by the (see Table 96 on page 139) and this endpoint interrupt is enabled by the UEPIEN Register UEPIEN (S:C2h) USB Endpoint Interrupt Enable Register (see Figure 102 on page 144). This bit is cleared by software. 0EP0INT Endpoint 0 Interrupt This bit is set by hardware when an interrupt is triggered by the (see Table 96 on page 139) and this endpoint interrupt is enabled by the UEPIEN Register UEPIEN (S:C2h) USB Endpoint Interrupt Enable Register (see Figure 102 on page 144). This bit is cleared by software. |
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