PLL1705

PLL1706

SLES046A – AUGUST 2002 – REVISED SEPTEMBER 2002

www.ti.com

8

THEORY OF OPERATION

MASTER CLOCK AND SYSTEM CLOCK OUTPUT

The PLL1705/6 consists of a dual PLL clock and master clock generator which generates four system clocks and two

buffered 27-MHz clocks from a 27-MHz master clock. Figure 7 shows the block diagram of the PLL1705/6. The PLL is

designed to accept a 27-MHz master clock.

PLL2

Counter N

Phase Detector

and

Loop Filter

OSC

Divider

SCKO3

384 fS

SCKO0–3

Frequency

Control

Counter M

VCO

Divider

PLL1

Counter M

Phase Detector

and

Loop Filter

Counter N

VCO

SCKO2

256 fS

Divider

SCKO1

33.8688/16.9344MHz

SCKO0

33.8688 MHz

MCKO2

27 MHz

MCKO1

27 MHz

XT1 XT2

Figure 7. Block Diagram