PLL1705

PLL1706

SLES046A – AUGUST 2002 – REVISED SEPTEMBER 2002

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13

Mode Register

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

0

1

1

1

0

0

CE6

CE5

CE4

CE3

CE2

CE1

RSV

SR

FS2

FS1

Table 6. Register Mapping

REGISTER

BIT NAME

DESCRIPTION

CE6

MCKO2 output enable/disable

CE5

MCKO1 output enable/disable

CE4

SCKO1 output enable/disable

CE3

SCKO3 output enable/disable

Mode control

CE2

SCKO2 output enable/disable

Mode control

CE1

SCKO0 output enable/disable

RSV

Reserved, must be 0

SR

Sampling rate select

FS[2:1]

Sampling frequency select

FS[2:1]: Sampling Frequency Group Select

FS2

FS1

SAMPLING FREQUENCY

DEFAULT

0

0

48 kHz

O

0

1

44.1 kHz

1

0

32 kHz

1

1

Reserved

SR: Sampling Rate Select

SR

SAMPLING RATE

DEFAULT

0

Standard

O

1

Double

CE [6:1]: Clock Output Control

CE1–CE6

CLOCK OUTPUT CONTROL

DEFAULT

0

Clock output disable

1

Clock output enable

O

While all the bits of CE [6:1] are 0, the PLL1706 goes into the power-down mode, all dynamic operation including PLLs

and the oscillator halt, but serial mode control is enabled for resumption.

CONNECTION DIAGRAM

Figure 14 shows the typical connection circuit for the PLL1705. There are four grounds for digital and analog power

supplies. However, the use of one common ground connection is recommended to avoid latch-up or other

power-supply-related troubles. Power supplies should be bypassed as close as possible to the device.

MPEG-2 APPLICATIONS

Typical applications for the PLL1705/6 are MPEG-2 based systems such as DVD players, DVD add-on cards for

multimedia PCs, digital HDTV systems, and set-top boxes. The PLL1705/6 provides audio system clocks for a CD-DA DSP,

DVD DSP, Karaoke DSP, and DAC(s) from a 27-MHz video clock.