PLL1705

PLL1706

SLES046A – AUGUST 2002 – REVISED SEPTEMBER 2002

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The master clock can be either a crystal oscillator placed between XT1 (pin 10) and XT2 (pin 11), or an external input to

XT1. If an external master clock is used, XT2 must be open. Figure 8 illustrates possible system clock connection options,

and Figure 9 illustrates the 27-MHz master clock timing requirement.

Crystal

PLL1705/PLL1706

Crystal

OSC

Circuit

27-MHz

Internal

Master

Clock

XT1

XT2

C2

C1

MCKO1

MCKO2

C1, C2 = 10 pF to 33 pF

Crystal Resonator Connection

PLL1705/PLL1706

XT1

XT2

MCKO1

MCKO2

External Clock Input Connection

External

Clock

Crystal

OSC

Circuit

27-MHz

Internal

Master

Clock

Figure 8. Master Clock Generator Connection Diagram

t(XT1H)

XT1

t(XT1L)

0.7 VCC

0.3 VCC

DESCRIPTION

SYMBOL

MIN

MAX

UNIT

Master clock pulse duration HIGH

10

ns

Master clock pulse duration LOW

10

ns

Figure 9. External Master Clock Timing Requirement

The PLL1705/6 provides a very low-jitter, high-accuracy clock. SCKO0 outputs a fixed 33.8688-MHz clock, SCKO1 outputs

clock output frequencies for programmed sampling frequencies are shown in Table 3.

Table 1. Generated System Clock SCKO1 Frequency

CSEL

SCKO1 FREQUENCY

LOW

33.8688 MHz

HIGH

16.9344 MHz

Table 2. Sampling Frequencies

SAMPLING RATE

SAMPLING FREQUENCY (kHz)

Standard sampling frequencies

32

44.1

48

Double sampling frequencies

64

88.2

96