ADT7301

Preliminary Technical Data

Rev. PrJ | Page 4 of 14

TIMING CHARACTERISTICS

and timed from a voltage level of 1.6 V.

Table 2.

Limit

Unit

Comments

5

ns min

CS to SCLK Setup Time

25

ns min

SCLK High Pulse Width

25

ns min

SCLK Low Pulse Width

35

ns max

Data Access Time after SCLK Falling Edge

20

ns min

Data Setup Time prior to SCLK Rising Edge

5

ns min

Data Hold Time after SCLK Rising Edge

5

ns min

CS to SCLK Hold Time

40

ns max

CS to DOUT High Impedance

1.6V

200

µA

200

TO

OUTPUT

PIN

50pF

Figure 2. Load Circuit for Data Access Time and Bus Relinquish Time