DP7140

7

generates the STOP condition, at which time if a nonvolatile

data register is being selected, the device begins an internal

programming cycle to non volatile memory. If the STOP

condition is not sent immediately after the last ACK the

internal non volatile programming cycle doesn t start.

While this internal cycle is in progress, the device will not

respond to any request from the Master device.

Write operations to volatile memory are completed during

the last bit of the data byte before the slave s acknowledge.

The device will be ready for another command only after a

STOP condition sent by Master.

Acknowledge Polling

The disabling of the inputs can be used to take advantage

of the typical write cycle time. Once the stop condition is

issued to indicate the end of the host s write operation, the

DP7140 initiates the internal write cycle. ACK polling can

be initiated immediately. This involves issuing the start

condition followed by the slave address. If the DP7140 is

still busy with the write operation, no ACK will be returned.

If the DP7140 has completed the write operation, an

acknowledge will be returned and the host can then proceed

with the next instruction operation.

WRITE Protection

The Write Protection feature allows the user to protect

against inadvertent programming of the non volatile data

registers. If the WP pin is tied to LOW, the data registers are

protected and become read only. Similarly, the WP pin going

low after start will interrupt a nonvolatile write to data

registers, while the WP pin going low after an internal write

cycle has started will have no effect on any write operation.

DP7140 will accept slave addresses but the data registers

are protected from programming, which the device indicates

by failing to send an acknowledge after data is received.

READ Operation

A Read operation with a designated address consists of a

three byte instruction followed by one or more Data Bytes

(See Figure 3). The master initiates the operation issuing a

START, an Identification byte with the R/W bit set to “0”, an

Address Byte. Then the master sends a second START, and

a second Identification byte with the R/W bit set to “1”. After

each of the three bytes, the DP7140 responds with an ACK.

Then DP7140 transmits the Data Byte. The master then can

continue the read operation with the content of the next

register by sending acknowledge or can terminate the read

operation by issuing a NoACK followed by a STOP

condition after the last bit of a Data Byte.

Table 13. MEMORY MAP

Address

Non volatile

Volatile

Register

Register

Default

Value

8

ACR

7

Reserved

6

General Purpose

00h

N/A

5

General Purpose

00h

N/A

4

General Purpose

00h

N/A

3

General Purpose

00h

N/A

2

General Purpose

00h

N/A

1

Device ID (read only)

D0h

N/A

0

IVR

80h

WR

If the master sends address 07h or addresses greater than

08h the slave responds with NoACK after the Memory

Address byte.

Address 8: Volatile Access Control Register

ACR (I/O)

The ACR bit 7 (VOL) toggles between Non volatile and volatile registers accessed at address 00h. When VOL is Low (0),

the non volatile IVR is accessed at address 00h. When VOL is high (1), the volatile Wiper Register is accessed at address 00h.

The initial default value for VOL = 0.

Bit

7

6

5

4

3

2

1

0

Name

0/1 VOL

0

0

0

0

0

0

0

00h and 80h are the only values that should be written to address 08h. For any other value written to address 08h the slave will

load only bit 7 but it will answer with a NoACK.

Address 7: RESERVED

The user should not read or write to this address. DP7140 will respond with NoACK and it will take no action.

Address 07h can be accessed only in a sequential read and its content is FFh.

Address 6 2: Non Volatile General Purpose Memory (I/O)

8 bit Non volatile Memory

Bit

7

6

5

4

3

2

1

0

Name

General Purpose Memories are preprogrammed at the factory to a default value of “00h”.