DP7140

6

Device Operation

serial interface logic, an 8 bit volatile wiper register, and six

8 bit, non volatile memory data registers. The resistor

array contains 255 separate resistive elements connected in

series. The physical ends of the array are equivalent to the

The tap positions between and at the ends of the series

CMOS transistor switches. Only one tap point for the

potentiometer is connected to the wiper terminal at a time

and is determined by the value of an 8 bit Wiper Register

(WR).

FFh

FEh

80h

01h

00h

When power is first applied to DP7140 the wiper is set

to midscale; Wiper Register = 80h. When the power supply

becomes sufficient to read the non volatile memory the

value stored in the Initial Value Register (IVR) is transferred

into the Wiper Register and the wiper moves to this new

position. Five additional 8 bit non volatile memory data

registers are provided for general purpose data storage. Data

can be read or written to the volatile or the non volatile

Serial Bus Protocol

The following defines the features of the 2 wire bus

protocol:

1. Data transfer may be initiated only when the bus is

not busy.

2. During a data transfer, the data line must remain

stable whenever the clock line is high. Any

changes in the data line while the clock is high

will be interpreted as a START or STOP condition.

The device controlling the transfer is a master, typically a

processor or controller, and the device being controlled is the

slave. The master will always initiate data transfers and

provide the clock for both transmit and receive operations.

Therefore, the DP7140 will be considered a slave device

in all applications.

START Condition

The START condition precedes all commands to the

device, and is defined as a HIGH to LOW transition of SDA

when SCL is HIGH. The DP7140 monitors the SDA and

SCL lines and will not respond until this condition is met.

STOP Condition

A LOW to HIGH transition of SDA when SCL is HIGH

determines the STOP condition. All operations must end

with a STOP condition.

Device Addressing

The bus Master begins a transmission by sending a

START condition. The Master then sends the address of the

particular slave device it is requesting. DP7140 has a fixed

Read/Write instruction bit. For a Read the value is “1” and

for Write the value is “0”.

After the Master sends a START condition and the slave

address byte, the DP7140 monitors the bus and responds

with an acknowledge (on the SDA line) when its address

matches the transmitted slave address.

Table 12. SALVE ADDRESS BIT FORMAT

B

S

L

B

S

M

0

1

0

1

0

0

0

R/W

Acknowledge (ACK)

After a successful data transfer, each receiving device is

required to generate an acknowledge. The Acknowledging

device pulls down the SDA line during the ninth clock cycle,

signaling that it received the 8 bits of data.

DP7140 responds with an acknowledge after receiving

a START condition and its slave address. If the device has

been selected along with a write operation, it responds with

an acknowledge after receiving each 8 bit byte. When the

DP7140 is in a READ mode it transmits 8 bits of data,

releases the SDA line, and monitors the line for an

acknowledge. Once it receives this acknowledge, the

DP7140 will continue to transmit data. If no acknowledge

is sent by the Master, the device terminates data transmission

and waits for a STOP condition.

WRITE Operation

In the Write mode, the Master device sends the START

condition and the slave address information to the Slave

device. In

s case the slave address also contains a

Read/Write command (R/W) on the last bit of the 1st byte.

After receiving an acknowledge from the Slave, the Master

device transmits a second byte containing a Memory

Address to select an available register. After a second

acknowledge is received from the Slave, the Master device

sends the data to be written into the selected register. The

DP7140 acknowledges once more and the Master