DP7140

9

Single write to either a volatile or non volatile register. Note that Bit 7 of ACR determines which memory type is being written.

Table 15. SINGLE WRITE

(1)

(2)

(3)

(4)

(5)

(6)

(7)

(9)

Start

Slave

Address

0

R/W

0

ACK

Memory

Address

0

ACK

Write

Data

0

ACK

Stop

A single write to either a volatile or non volatile register. At address 00h bit 7 of ACR determines which memory type is being written.

Table 16. MULTIPLE WRITES

(1)

(2)

(3)

(4)

(5)

(6)

(7)

(8)

(9)

Start

Slave

Address

0

R/W

0

ACK

Memory

Address

0

ACK

Write

Data

0

ACK

Write

Data

0

ACK

Stop

Multiple writes are possible only if the starting address is 08h and it should be stopped with the first nonvolatile data byte. If

a nonvolatile write does not end with a STOP procedure the register is not written.

(B) Read data procedure with designated address.

1. Host transfers the start condition

2. Host transfers the device slave address with the write mode R/W bit (0)

3. ACK signal recognition from the device

4. Host transfers the read address

5. ACK signal recognition from the device

6. Host transfers the re start condition

7. Host transfers the slave address with the read mode R/W bit (1).

8. ACK signal recognition from the device

9. The device transfers the read data from the designated address

10. Host transfers ACK signal

11. The (9) & (10) routines above are repeated if needed, and the read address is auto incremented

12. Host transfers ACK H to the device

13. Host transfers the stop condition

Table 17. READ DATA

(1)

(2)

(3)

(4)

(5)

(6)

(7)

(8)

(9)

(10)

(11)

(12)

(13)

Start

Slave

Address

0

R/W

0

ACK

Memory

Address

0

ACK

Restart

Slave

Address

1

R/W

0

ACK

Read

Data

0

ACK

Read

Data

1

ACK

Stop

(C) Read data procedure without a designated address.

1. Host transfers the start condition

2. Host transfers the device slave address with the read mode R/W bit =1

3. ACK signal recognition from the device. (Host then changes to receiver)

4. The device transfers data from the previous access address +1

5. Host transfers ACK signal

6. The (4) & (5) routines above are repeated if needed

7. Host transfers AC

8. Host transfers the stop condition

Table 18. Read Data w/o Designated Address

(1)

(2)

(3)

(4)

(5)

(6)

(7)

(8)

Start

Slave

Address

1

R/W

0

ACK

Read

Data

0

ACK

Read

Data

1

ACK

Stop