MCP3913 datasheet(61/82 Pages) MICROCHIP

61 / 82 page

 2013 Microchip Technology Inc.

DS20005227A-page 61

MCP3913

8.3

PHASE0 Register – Phase

Configuration Register for

Channel Pair 4/5

Any write to this register automatically resets and

restarts all active ADCs.

Name

Bits

Address

Cof.

PHASE0

0x09

R/W

PHASE0 REGISTER

U-0

——

—

bit 23

bit 16

U-0

R/W-0

—

PHASEC<11>

PHASEC<10>

PHASEC<9>

PHASEC<8>

bit 15

bit 8

R/W-0

PHASEC<7>

PHASEC<6>

PHASEC<5>

PHASEC<4>

PHASEC<3>

PHASEC<2>

PHASEC<1>

PHASEC<0>

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 23-12

Unimplemented:

Read as 0

bit 11-0

PHASEC<11:0>

Phase delay between channels CH4 and CH5 (reference). Delay = PHASEC<11:0>

decimal code/DMCLK

MCP3913 Datasheet(PDF) 61 Page - Microchip Technology

MCP3913 Datasheet(HTML) 61 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82

Datasheet Download

Link URL