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ML7005 Datasheet(PDF) 13 Page - LAPIS Semiconductor Co., Ltd. |
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ML7005 Datasheet(HTML) 13 Page - LAPIS Semiconductor Co., Ltd. |
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13 / 26 page  FEDL7005-01 ML7005 13/25 Processor Interface Charactceristics (Intel Processor Mode) (VDD=+2.7 to +5.5 V, Ta=-30 to +85°C) Parameter Symbol Condition Min. Typ. Max. Unit Address Data Setup Time tAL — 80 — — ns Address Data Hold Time tLA — 30 — — ns ALE Signal Time tLL — 80 — — ns Chip Select Setup Time before Read tCRS — 30 — — ns Chip Select Hold Time after Read tCRH — 30 — — ns READB Data Output Delay Time tRD VOL 0.4 V, VOH VDD – 0.4 V 0 90 180 ns Data Float Time after Read tRDF — 5 37 60 ns READB Signal Time tRW — 200 — — ns Chip Select Setup Time before Write tCWS — 30 — — ns Chip Select Hold Time after Write tCWH — 30 — — ns WRB Signal Time tWW — 140 — — ns Data Setup Time before Write tDW — 80 — — ns Data Hold Time tWD — 30 — — ns |
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