ML7005 datasheet(5/26 Pages) LAPIS

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FEDL7005-01

ML7005

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Symbol

Type

Description

READB

Input pin for processor interface.

When PTYPE is "1" (Intel processor mode) :

This pin is the read control input pin.

When this pin is set to "0", data in the specified register is output to the

bus lines (D3 to D0).

At that time, CSB must be "0".

See the figure 4 for processor interface timing.

When PTYPE is "0" (Motorola processor mode) :

This pin is the clock input pin (equivalent to SCLK of the MSM7524).

When in Write mode, data in D3 to D0 is written to the specified register

at the falling edge of the READB signal.

When in Read mode, data in the specified register is output to D3 to D0

when the READB signal is "1", and D3 to D0 is opened when the

READB signal is "0".

The READB signal is not necessarily a periodical signal.

See the figure 5 for processor interface timing.

CSB

Chip select input pin for processor interface.

When the CSB signal is "0", read and write operations are possible.

When the CSB signal is "1", read and write operations are impossible.

ALE

Input pin for processor interface.

When PTYPE is "1" (Intel processor mode) :

This pin is the address latch enable input pin.

The register address data in D1 to D0 is latched at the falling edge of

ALE.

When PTYPE is "0" (Motorola processor mode) :

This pin is the address data input pin (equivalent to AD0 of the

MSM7524).

When this pin is "1", data can be written to the control register (CR) and

data can be read from the status register (STR).

When this pin is "0", data can be written to the DTMF transmit register

(DTMFT) and data can be read from the DTMF receive register

(DTMFR).

WRB

Input pin for processor interface.

When PTYPE is "1" (Intel processor mode) :

This pin is the Write control input.

Data in the data bus lines (D3 to D0) is written to the specified register.

At that time, CSB must be "0".

When PTYPE is "0" (Motorola processor mode) :

This is the signal input pin for controlling the Read and Write modes

(equivalent to R/W of the MSM7524).

When this pin is "1", the LSI enters the Read mode.

When this pin is "0", the LSI enters the Write mode.

D3 to D0

18 to 21

I/O

4-bit data bus I/O pins for processor interface.

When PTYPE is "1" (Intel processor mode), D1 and D0 are also used for

addressing.

ML7005 Datasheet(PDF) 5 Page - LAPIS Semiconductor Co., Ltd.

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