PC87373 datasheet(48/174 Pages) NSC

48 / 174 page

3.0 Device Architecture and Configuration (Continued)

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Revision 1.1

3.7.7

SuperI/O Revision ID Register (SRID)

This register contains the ID number of the specific family member (Chip ID) and the chip revision number (Chip Rev). The

PC87373 is identified by the value ‘000’. The Chip Rev is incremented on each revision.

Power Well: VSB3

Location:

Index 27h

Type:

3.7.8

Clock Generator Control Register (CLOCKCF)

Power Well: VSB3

Location:

Index 29h

Type:

Varies per bit

Bit

76543210

Name

Chip ID

Chip Rev

Reset

XXXXX

Bit

Description

7-5

Chip ID. These bits identify a specific device of a family.

4-0

Chip Rev. These bits identify the device revision.

Bit

43210

Name

HFCGEN

Reserved

CKVALID

Reserved

Reset

00000

Bit

Type

Description

R/W1S HFCGEN (Clock Generator Enable). When set to 1, this bit enables the operation of the Clock

Generator, and locks the configuration register CLOCKCF by disabling writing to all its bits (including to

the HFCGEN bit itself). Once set, this bit can be cleared by VDD3 Power-Up reset (or Hardware reset).

0: Clock Generator disabled; the R/W bits are enabled for write (default).

1: Clock Generator enabled; all the bits are RO.

6-5

−

Reserved.

4RO

CKVALID (Valid Clock Generator, Clock Status). This bit indicates the status of the on-chip, 48 MHz

Clock Generator and controls the generator output clock signal. The PC87373 modules using this clock

may be enabled (see Section 3.3.1 on page 40) only after this bit is read high (generator clock is valid).

0: Generator output clock frozen (default)

1: Generator output clock active (stable and toggling)

3-0

−

Reserved.

PC87373 Datasheet(PDF) 48 Page - National Semiconductor (TI)

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