SST25WF080B datasheet(5/39 Pages) MICROCHIP

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 2014 Microchip Technology Inc.

DS20005164C-page 5

SST25WF080B

3.0

MEMORY ORGANIZATION

The SST25WF080B SuperFlash memory arrays are

organized in 256 uniform 4 KByte sectors, with 16

64 KByte overlay erasable blocks.

FIGURE 3-1:

MEMORY MAP

4.0

DEVICE OPERATION

SST25WF080B is accessed through the SPI (Serial

Peripheral Interface) bus compatible protocol. The SPI

bus consist of four control lines; Chip Enable (CE#) is

used to select the device, and data is accessed through

the Serial Data Input (SI), Serial Data Output (SO), and

Serial Clock (SCK).

The SST25WF080B supports both Mode 0 (0,0) and

Mode 3 (1,1) of SPI bus operations. The difference

between the two modes, as shown in Figure 4-1, is the

state of the SCK signal when the bus master is in

Stand-by mode and no data is being transferred. The

SCK signal is low for Mode 0 and SCK signal is high for

Mode 3. For both modes, the Serial Data In (SI) is sam-

pled at the rising edge of the SCK clock signal and the

Serial Data Output (SO) is driven after the falling edge

of the SCK clock signal.

FIGURE 4-1:

SPI PROTOCOL

25164 F51.0

Top of Memory Block

00FFFFH

00F000H

000FFFH

000000H

001FFFH

001000H

Bottom of Memory Block

01FFFFH

01F000H

01FFFFH

010000H

0FFFFFH

0FF000H

0F0FFFH

0F0000H

Number of Sectors

255

240

Number of 64 KByte

Blocks

25164 F03.0

MODE 3

SCK

CE#

MODE 3

DON T CARE

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

MODE 0

HIGH IMPEDANCE

MSB

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