SST25WF080B datasheet(12/39 Pages) MICROCHIP

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SST25WF080B

DS20005164C-page 12

 2014 Microchip Technology Inc.

5.4

Fast-Read Dual I/O (40 MHz)

The Fast-Read Dual I/O (BBH) instruction reduces the

total number of input clock cycles, which results in

faster data access. The device is first selected by driv-

ing Chip Enable CE# low. Fast-Read Dual I/O is initi-

ated by executing an 8-bit command (BBH) on SI/SIO0,

thereafter, the device accepts address bits A23-A0 and

a dummy byte on SI/SIO0 and SO/SIO1. It offers the

capability to input address bits A23-A0 at a rate of two

bits per clock. Odd address bits A23 through A1 are

input on SIO1 and even address bits A22 through A0

are input on SIO0, alternately For example, the most

significant bit is input first followed by A23/22, A21/A20,

and so on. Each bit is latched at the same rising edge

of the Serial Clock (SCK). The input data during the

dummy clocks is “don’t care”. However, the SIO0 and

SIO1 pin must be in high-impedance prior to the falling

edge of the first data output clock.

Following a dummy cycle, the Fast-Read Dual I/O

instruction outputs the data starting from the specified

address location on the SIO1 and SIO0 lines. SIO1 out-

puts, per clock sequence, odd data bits D7, D5, D3,

and D1; and SIO0 outputs even data bits D6, D4, D2,

and D0 per clock edge. CE# must remain active low for

the duration of the Fast-Read Dual I/O instruction

cycle. The data output stream is continuous through all

addresses until terminated by a low-to-high transition

on CE#.

The internal address pointer will automatically incre-

ment until the highest memory address is reached.

Once the highest memory address is reached, the

address pointer automatically increments to the begin-

ning (wraparound) of the address space. For example,

once the data from address location FFFFFH is read,

the next output is from address location 000000H. See

Figure 5-4 for the Fast-Read Dual I/O sequence.

FIGURE 5-4:

FAST-READ DUAL I/O SEQUENCE

25134 F53.0

CE#

SIO1

SIO0

SCK

012 34 5 6 7 8 910 11 12 13 14

MODE 3

MODE 0

15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38

0 64

3 1

MSB

0 64

3 1

MSB

A23-16

A15-8

A7-0

DOUT

N+1

N+2

N+3

IO, Switches from Input to Output

Dummy

Cycle

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