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SST25VF080B Datasheet(PDF) 5 Page - Microchip Technology

Part # SST25VF080B
Description  8 Mbit SPI Serial Flash
PDF  32 Pages
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Manufacturer  MICROCHIP [Microchip Technology]
Direct Link  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

SST25VF080B Datasheet(HTML) 5 Page - Microchip Technology

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 2015 Microchip Technology Inc.
DS20005045C-page 5
SST25VF080B
4.2
Write Protection
SST25VF080B provides software Write protection. The
Write Protect pin (WP#) enables or disables the lock-
down function of the status register. The Block-Protec-
tion bits (BP3, BP2, BP1, BP0, and BPL) in the status
register provide Write protection to the memory array
and the status register. See Table 4-3 for the Block-Pro-
tection description.
4.2.1
WRITE PROTECT PIN (WP#)
The Write Protect (WP#) pin enables the lock-down
function of the BPL bit (bit 7) in the status register.
When WP# is driven low, the execution of the Write-
Status-Register (WRSR) instruction is determined by
the value of the BPL bit (see Table 4-1). When WP# is
high, the lock-down function of the BPL bit is disabled.
4.3
Status Register
The software status register provides status on
whether the flash memory array is available for any
Read or Write operation, whether the device is Write
enabled, and the state of the Memory Write protection.
During an internal Erase or Program operation, the sta-
tus register may be read only to determine the comple-
tion of an operation in progress. Table 4-2 describes
the function of each bit in the software status register.
4.3.1
BUSY
The Busy bit determines whether there is an internal
Erase or Program operation in progress. A “1” for the
Busy bit indicates the device is busy with an operation
in progress. A “0” indicates the device is ready for the
next valid operation.
4.3.2
WRITE ENABLE LATCH (WEL)
The Write-Enable-Latch bit indicates the status of the
internal memory Write Enable Latch. If the Write-
Enable-Latch bit is set to “1”, it indicates the device is
Write enabled. If the bit is set to “0” (reset), it indicates
the device is not Write enabled and does not accept
any memory Write (Program/Erase) commands. The
Write-Enable-Latch bit is automatically reset under the
following conditions:
•Power-up
• Write-Disable (WRDI) instruction completion
• Byte-Program instruction completion
• Auto Address Increment (AAI) programming is
completed or reached its highest unprotected
memory address
• Sector-Erase instruction completion
• Block-Erase instruction completion
• Chip-Erase instruction completion
• Write-Status-Register instructions
TABLE 4-1:
CONDITIONS TO EXECUTE WRITE-STATUS-REGISTER (WRSR) INSTRUCTION
WP#
BPL
Execute WRSR Instruction
L1
Not Allowed
L0
Allowed
HX
Allowed
TABLE 4-2:
SOFTWARE STATUS REGISTER
Bit
Name
Function
Default at
Power-up
Read/Write
0
BUSY
1 = Internal Write operation is in progress
0 = No internal Write operation is in progress
0R
1
WEL
1 = Device is memory Write enabled
0 = Device is not memory Write enabled
0R
2
BP0
Indicate current level of block write protection (See Table 4-3)
1R/W
3
BP1
Indicate current level of block write protection (See Table 4-3)
1R/W
4
BP2
Indicate current level of block write protection (See Table 4-3)
1R/W
5
BP3
Indicate current level of block write protection (See Table 4-3)
0R/W
6
AAI
Auto Address Increment Programming status
1 = AAI programming mode
0 = Byte-Program mode
0R
7
BPL
1 = BP3, BP2, BP1, BP0 are read-only bits
0 = BP3, BP2, BP1, BP0 are read/writable
0R/W



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