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NSC800 Datasheet(PDF) 52 Page - National Semiconductor (TI) |
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NSC800 Datasheet(HTML) 52 Page - National Semiconductor (TI) |
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52 / 76 page  1212 InputOutput IN A (n) Input data to the Accumulator from the IO device at ad- dress N A w (n) No flags affected 76543210 11011011 n Timing M cycles 3 T states 11 (4 3 4) Addressing Mode Source Direct Destination Register IN r (C) Input data to register r from the IO device addressed by the contents of register C If re110 only flags are affected r w (C) S Set if result is negative Z Set if result is zero H Reset PV Set if result parity is even N Reset C NA 76543210 11101101 01 r 000 Timing M cycles 3 T states 12 (4 4 4) Addressing Mode Source Register Indirect Destination Register OUT (C) r Output register r to the IO device addressed by the con- tents of register C (C) w r No flags affected 76543210 11101101 01 r 001 Timing M cycles 3 T states 12 (4 4 4) Addressing Mode Source Register Destination Register Indirect INI Input data from the IO device addressed by the contents of register C to the memory location pointed to by the contents of the HL register The HL pointer is incremented and the byte counter B is decremented (HL) w (C) S Undefined B w B b 1 Z Set if Bb1e0 otherwise reset HL w HL a 1 H Undefined PV Undefined N Set C NA 76543210 11101101 10100010 Timing M cycles 4 T states 16 (4 5 3 4) Addressing Mode ImpliedSource Register In- direct Destination Register Indirect OUTI Output data from memory location (HL) to the IO device at port address (C) increment the memory pointer and decre- ment the byte counter B (C) w (HL) S Undefined B w B b 1 Z Set if Bb1e0 otherwise reset HL w HL a 1 H Undefined PV Undefined N Set C NA 76543210 11101101 10100011 Timing M cycles 4 T states 16 (4 5 3 4) Addressing Mode ImpliedSource Register In- direct Destination Register Indirect IND Input data from IO device at port address (C) to memory location (HL) and decrement HL memory pointer and byte counter B (HL) w (C) S Undefined HL w HL b 1 Z Set if Bb1e0 otherwise reset B w B b 1 H Undefined PV Undefined N Set C NA 76543210 11101101 10101010 Timing M cycles 4 T states 16 (4 5 3 4) Addressing Mode ImpliedSource Register In- direct Destination Register Indirect 52 |
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