NSC800 datasheet(16/76 Pages) NSC

Part #	NSC800

Description	NSC800TM High-Performance Low-Power CMOS Microprocessor

PDF	76 Pages

Scroll/Zoom	100%

Manufacturer	NSC [National Semiconductor (TI)]

Direct Link	http://www.national.com

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16 / 76 page

90 Timing and Control (Continued)

92 CPU TIMING

The NSC800 uses a multiplexed bus for data and address-

es The 16-bit address bus is divided into a high-order 8-bit

address bus that handles bits 8 – 15 of the address and a

low-order 8-bit multiplexed addressdata bus that handles

bits 0 – 7 of the address and bits 0 – 7 of the data Strobe

outputs from the NSC800 (ALE RD and WR) indicate when

a valid address or data is present on the bus IOM indi-

cates whether the ensuing cycle accesses memory or IO

During an input or output instruction the CPU duplicates the

lower half of the address AD(0 – 7) onto the upper address

bus A(8 – 15)

The eight bits of address will stay on A(8 –

15) for the entire machine cycle and can be used for chip

selection directly

Figure 9 illustrates the timing relationship for opcode fetch

cycles with and without a wait state

TLC5171 – 15

FIGURE 9a Opcode Fetch Cycles without WAIT States

TLC5171 – 16

FIGURE 9b Opcode Fetch Cycles with WAIT States

NSC800 Datasheet(PDF) 16 Page - National Semiconductor (TI)