L99MC6GJ datasheet(27/55 Pages) STMICROELECTRONICS

27 / 55 page

DocID026835 Rev 3

27/55

L99MC6GJ

Functional description of the SPI

8.1

Signal description

8.1.1

Serial clock (SCK)

This input signal provides the timing of the serial interface. Data present at serial data input

(SDI) is latched on the rising edge of serial clock (SCK). Data on serial data output (SDO) is

shifted out at the falling edge of serial clock (see Figure 11).

The SPI can be driven by a microcontroller with its SPI peripherals running in following

mode: CPOL = 0 and CPHA = 0 (see Figure 11).

8.1.2

Serial data input (SDI)

This input is used to transfer data serially into the device. It receives the data to be written.

Values are latched on the rising edge of serial clock (SCK).

8.1.3

Serial data output (SDO)

This output signal is used to transfer data serially out of the device. Data is shifted out on the

falling edge of serial clock (SCK).

DO also reflects the status of the <Global Error Flag> (<Global Status Register>, bit 7) while

CSN is low and no clock signal is present

8.1.4

Chip select not (CSN)

When this input signal is high, the device is deselected and serial data output (SDO) is high-

impedance. Driving this input low enables the communication. The communication must

start and stop on a low-level of serial clock (SCK).

Figure 11. Clock polarity and clock phase

L99MC6GJ Datasheet(PDF) 27 Page - STMicroelectronics