Operation description

SRK2001A

10/20

DocID029495 Rev 1

7.2

Turn-on

The turn-on logic is such that each SR MOSFET is switched on when the sensed drain-

10% of the clock cycle).

Figure 5. Typical waveforms

capacitive currents (due to secondary side parasitic capacitance and not really related to the

current flowing through the MOSFET body diode. Figure 6 shows the effect of this parasitic:

in case at the reduced load a capacitive current spike should trigger the turn-on, there would

be a current inversion (flowing from the output capacitor toward the SR MOSFET). This

current inversion would cause a discharge of the output capacitor and consequently an

increase of the rectified current rms value, in order to balance that dis-charge; this, in turn,

would affect a bit the converter efficiency.

In case of SR MOSFETs with low parasitic capacitance, capacitive currents lasting less than

10% of the clock cycle are filtered: the gate drive of course will go high when the current

really flows through the body diode (i.e. the comparator sensing DVS1,2 signal and

parasitic capacitance, capacitive currents lasting more than 10% of the clock cycle cannot

be filtered by the turn-on delay and premature turn-on will be present.