STMPE812A datasheet(9/53 Pages) STMICROELECTRONICS

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STMPE812A

I2C interface

Doc ID 18225 Rev 4

9/53

2.1

I2C features

The features that are supported by the I2C interface are listed below:

●

I2C slave device

●

Operates at VCC (1.65 V - 3.6 V)

●

Compliant to Philips I2C specification version 2.1

●

Supports standard (up to 100 Kbps) and fast (up to 400 Kbps) modes

●

I2C address in 0x41 (0x82/83 including Rd/Wr bit) or 0x40 (0x80/81 including Rd/Wr

bit)

The slave address is selected by the state of P0 pin. The state of the pin is read upon reset

and then the pin can be configured for normal operation. The pin shall have an external pull-

up or pull-down to set the address.

Start condition

A Start condition is identified by a falling edge of SDATA while SCLK is stable at high state.

A Start condition must precede any data/command transfer. The device continuously

monitors for a Start condition and does not respond to any transaction unless one is

encountered.

Stop condition

A Stop condition is identified by a rising edge of SDATA while SCLK is stable at high state. A

Stop condition terminates communication between the slave device and the bus master. A

read command that is followed by NoAck can be followed by a Stop condition to force the

slave device into idle mode. When the slave device is in idle mode, it is ready to receive the

next I2C transaction. A Stop condition at the end of a write command stops the write

operation to registers.

Acknowledge bit

The acknowledge bit is used to indicate a successful byte transfer. The bus transmitter

releases the SDATA after sending eight bits of data. During the ninth bit, the receiver pulls

the SDATA low to acknowledge the receipt of the eight bits of data. The receiver may leave

the SDATA in high state if it does not acknowledge the receipt of the data.

2.2

Data input

The device samples the data input on SDATA on the rising edge of the SCLK. The SDATA

signal must be stable during the rising edge of SCLK and the SDATA signal must change

only when SCLK is driven low.

Table 4.

Slave address

ADDR (P0)

7-bit I2C slave address

040h

141h

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