MPC9774

TIMING SOLUTIONS

7

MOTOROLA

Table 9. DC Characteristics (VCC = 2.5V ± 5%, TA = 0°C to + 85°C)

Symbol

Characteristics

Min

Typ

Max

Unit

Condition

VCC_PLL

PLL supply voltage

2.325

VCC

V

LVCMOS

VIH

Input high voltage

1.7

VCC + 0.3

V

LVCMOS

VIL

Input low voltage

-0.3

0.7

V

LVCMOS

VOH

Output High Voltage

1.8

V

IOH =-15 mAa

VOL

Output Low Voltage

0.6

V

IOL = 15 mA

ZOUT

Output impedance

17 - 20

W

IIN

Input Currentb

±200

µA

VIN = VCC or GND

ICC_PLL

Maximum PLL Supply Current

2.0

5.0

mA

VCCA Pin

ICC

Maximum Quiescent Supply Current

1.0

mA

All VCC Pins

a.

The MPC9774 is capable of driving 50

Ω transmission lines on the incident edge. Each output drives one 50Ω parallel terminated

transmission line to a termination voltage of VTT. Alternatively, the device drives up to two 50Ω series terminated transmission lines per

output.

b.

Inputs have pull-down or pull-up resistors affecting the input current.

Table 10. AC Characteristics (VCC = 2.5V ± 5%, TA = 0°C to + 85°C)a b

Symbol

Characteristics

Min

Typ

Max

Unit

Condition

fref

Input reference frequency

÷8 feedback

÷12 feedback

÷16 feedback

÷24 feedback

÷32 feedback

÷48 feedback

Input reference frequency in PLL bypass modec

25.0

16.6

12.5

8.33

6.25

4.16

50.0

33.3

25.0

16.6

12.5

8.3

TBD

MHz

MHz

MHz

MHz

MHz

MHz

MHz

PLL locked

PLL bypass

fVCO

VCO frequency ranged

200

400

MHz

fMAX

Output Frequency

÷4 output

÷8 output

÷12 output

÷16 output

÷24 output

50.0

25.0

16.6

12.5

8.33

100.0

50.0

33.3

25.0

16.6

MHz

MHz

MHz

MHz

MHz

PLL locked

frefDC

Reference Input Duty Cycle

40

60

%

tr, tf

CCLKx Input Rise/Fall Time

1

ns

0.7 to 1.7V

t(

∅)

Propagation Delay (static phase offset)

CCLKx or PCLK to FB_IN

±150

ps

PLL locked

tsk(O)

Output-to-output Skewe

300

ps

DC

Output duty cycle

45

50

55

%

tr, tf

Output Rise/Fall Time

0.1

1.0

ns

0.6 to 1.8V

tPLZ, HZ

Output Disable Time

10

ns

tPZL, LZ

Output Enable Time

10

ns

tJIT(CC)

Cycle-to-cycle jitter

RMS (1

σ)f

TBD

ps

tJIT(PER) Period Jitter

RMS (1

σ)

TBD

ps

tJIT(

∅)

I/O Phase Jitter

RMS (1

σ)

TBD

ps

BW

PLL closed loop bandwidthg

TBD

kHz

tLOCK

Maximum PLL Lock Time

10

ms

a.

All AC characteristics are design targets and subject to change upon device characterization.

b.

AC characteristics apply for parallel output termination of 50

Ω to VTT.

c.

In bypass mode, the MPC9774 divides the input reference clock.

d.

The input reference frequency must match the VCO lock range divided by the total feedback divider ratio: fref = fVCO ÷ (M ⋅ VCO_SEL).

e.

See application section for part-to-part skew calculation.

f.

See application section for a jitter calculation for other confidence factors than 1

σ.

g.

-3 dB point of PLL transfer characteristics.