MPC9774

TIMING SOLUTIONS

3

MOTOROLA

Table 1. PIN CONFIGURATION

Pin

I/O

Type

Function

CCLK0

Input

LVCMOS

PLL reference clock

CCLK1

Input

LVCMOS

Alternative PLL reference clock

FB_IN

Input

LVCMOS

PLL feedback signal input, connect to QFB

CCLK_SEL

Input

LVCMOS

LVCMOS clock reference select

VCO_SEL

Input

LVCMOS

VCO operating frequency select

PLL_EN

Input

LVCMOS

PLL enable/PLL bypass mode select

MR/OE

Input

LVCMOS

Output enable/disable (high-impedance tristate) and device reset

CLK_STOP

Input

LVCMOS

Output enable/clock stop (logic low state)

FSEL_A

Input

LVCMOS

Frequency divider select for bank A outputs

FSEL_B

Input

LVCMOS

Frequency divider select for bank B outputs

FSEL_C

Input

LVCMOS

Frequency divider select for bank C outputs

FSEL_FB[1:0]

Input

LVCMOS

Frequency divider select for the QFB output

QA[4:0]

Output

LVCMOS

Clock outputs (Bank A)

QB[4:0]

Output

LVCMOS

Clock outputs (Bank B)

QC[3:0]

Output

LVCMOS

Clock outputs (Bank C)

QFB

Output

LVCMOS

PLL feedback output. Connect to FB_IN.

GND

Supply

Ground

Negative power supply

VCC_PLL

Supply

VCC

PLL positive power supply (analog power supply). It is recommended to use an external RC filter

for the analog power supply pin VCC_PLL. Please see applications section for details.

VCC

Supply

VCC

Positive power supply for I/O and core. All VCC pins must be connected to the positive power

supply for correct operation

Table 2. Function Table (MPC9774 configuration controls)

Control

Default

0

1

CCLK_SEL

0

Selects CCLK0 as PLL refererence signal input

Selects CCKL1 as PLL reference signal input

VCO_SEL

0

Selects VCO

÷ 2. The VCO frequency is scaled by a

factor of 2 (high input frequency range)

Selects VCO

÷ 4. The VCO frequency is scaled by a

factor of 4 (low input frequency range).

PLL_EN

1

Test mode with the PLL bypassed. The reference clock is

substituted for the internal VCO output. MPC9774 is fully

static and no minimum frequency limit applies. All PLL

related AC characteristics are not applicable.

Normal operation mode with PLL enabled.

CLK_STOP

1

QA, QB an QC outputs disabled in logic low state. QFB

is not affected by CLK_STOP. CLK_STOP deassertion

may cause the initial output clock pulse to be distorted.

Outputs enabled (active)

MR/OE

1

Outputs disabled (high-impedance state) and reset of the

device. During reset/output disable the PLL feedback

loop is open and the internal VCO is tied to its lowest

frequency. The MPC9774 requires reset after any loss of

PLL lock. Loss of PLL lock may occur when the external

feedback path is interrupted. The length of the reset

pulse should be greater than one reference clock cycle

(CCLKx). The device is reset by the internal power–on

reset (POR) circuitry during power–up.

Outputs enabled (active)

VCO_SEL, FSEL_A, FSEL_B, FSEL_C and FSEL_FB[1:0] control the operating PLL frequency range and input/output frequency ratios.