MPC9774

MOTOROLA

TIMING SOLUTIONS

12

Figure 12. Output–to–output Skew tSK(O)

Figure 13. Propagation delay (t(

∅), static phase

offset) test reference

Figure 14. Output Duty Cycle (DC)

The pin–to–pin skew is defined as the worst case difference in

propagation delay between any similar delay path within a

single device

The time from the PLL controlled edge to the non controlled

edge, divided by the time between PLL controlled edges,

expressed as a percentage

VCC

VCCB2

GND

VCC

VCCB2

GND

tSK(O)

VCC

VCCB2

GND

tP

T0

DC = tP/T0 x 100%

VCC

VCCB2

GND

VCC

VCCB2

GND

t(

∅)

CCLKx

FB_IN

TJIT(

∅) = |T0–T1mean|

CCLKx

FB_IN

The deviation in t0 for a controlled edge with respect to a t0 mean in a

random sample of cycles

Figure 15. I/O Jitter

Figure 16. Cycle–to–cycle Jitter

Figure 17. Period Jitter

The variation in cycle time of a signal between adjacent cycles, over a

random sample of adjacent cycle pairs

The deviation in cycle time of a signal with respect to the ideal period over

a random sample of cycles

TN

tJIT(CC) = |TN – TN + 1|

TN+1

tJIT(PER) =|TN –(1÷f0)|

T0

tF

tR

VCC=3.3V VCC= 2.5V

2.4

1.8V

0.55

0.6V

Figure 18. Output Transition Time Test Reference