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WM8773

PP Rev 1.0 June 2002

19

Control bit MS selects between audio interface Master and Slave Modes. In Master mode ADCLRC

and BCLK are outputs and are generated by the WM8773. In Slave mode ADCLRC and BCLK are

inputs to WM8773.

REGISTER ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

10111

Interface Control

8

MS

0

Audio Interface Master/Slave Mode

select:

0 : Slave Mode

1: Master Mode

MASTER MODE ADCLRC FREQUENCY SELECT

In Master mode the WM8773 generates ADCLRC and BCLK. These clocks are derived from master

clock and the ratio of MCLK to ADCLRC and are set by ADCRATE.

REGISTER ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

0111 ADCLRC frequency

select

2:0

ADCRATE[2:0]

010

Master Mode MCLK:ADCLRC

ratio select:

010: 256fs

011: 384fs

100: 512fs

101: 768fs

ADC OVERSAMPLING RATE SELECT

For ADC operation at 96kHz it is recommended that the user set the ADCOSR bit. This changes the

ADC signal processing oversample rate to 64fs.

REGISTER ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

10111

ADC Oversampling Rate

3

ADCOSR

0

ADC oversampling rate select

0: 128x oversampling

1: 64x oversampling

MUTE MODES

Each ADC channel has an individual mute control bit, which mutes the input to the ADC. In addition

both channels may be muted by setting ADCMUTE.

REGISTER ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

11001

ADC Mute

7

ADCMUTE

0

ADC MUTE Left and Right

0 : Normal Operation

1: mute ADC left and ADC

right

11001

ADC Mute Left

5

MUTE

0

ADC Mute select

0 : Normal Operation

1: mute ADC left

11010

ADC Mute Right

5

MUTE

0

ADC Mute select

0 : Normal Operation

1: mute ADC right

The Record outputs may be enabled by setting RECEN, where RECEN enables the RECL and

RECR outputs.

REGISTER ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

10100

REC Enable

5

RECEN

0

REC Output Enable

0 : REC output muted

1: REC output enabled