WM8773 datasheet(23/29 Pages) WOLFSON

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WM8773

PP Rev 1.0 June 2002

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

10100

Mute

RECEN

REC Output Enable

0 : REC output muted

1: REC output enabled

1:0

FMT[1:0]

Interface format select

00: right justified mode

01: left justified mode

10: I

2S mode

11: DSP mode

ADCLRC Polarity or DSP Early/Late mode select

LRP

Left Justified / Right Justified /

0: Standard ADCLRC Polarity

1: Inverted ADCLRC Polarity

DSP Mode

0: Early DSP mode

1: Late DSP mode

BCP

BITCLK Polarity

0: Normal - ADCLRC sampled on rising edge of BCLK;

DOUT changes on falling edge of BCLK.

1: Inverted - ADCLRC sampled on falling edge of BCLK;

DOUT changes on rising edge of BCLK.

5:4

WL[1:0]

Input Word Length

00: 16-bit Mode

01: 20-bit Mode

10: 24-bit Mode

11: 32-bit Mode (not supported in right justified mode)

10110

Interface

Control

ADCHPD

ADC Highpass Filter Disable:

0: Highpass Filter enabled

1: Highpass Filter disabled

2:0

ADCRATE[2:0]

010

Master Mode MCLK:ADCLRC ratio select:

010: 256fs

011: 384fs

100: 512fs

ADCOSR

ADC oversample rate select

0: 128x oversampling

1: 64x oversampling

10111

Master Mode

control

Maser/Slave interface mode select

0: Slave Mode – ADCLRC and BCLK are inputs

1: Master Mode – ADCLRC and BCLK are outputs

PWDN

Chip Powerdown Control (works in together with ADCD)

0: All circuits running, outputs are active

1: All circuits in power save mode, outputs muted

11000

Powerdown

Control

ADCD

ADC powerdown:

0: ADC enabled

1: ADC disabled

4:0

LAG[4:0]

01100

(0dB)

Attenuation data for left channel ADC gain in 1dB steps

MUTE

Mute for Left channel ADC:

0: Mute off

1: Mute on

LRBOTH

Setting LRBOTH will write the same gain value to LAG[4:0] and

RAG[4:0]

11001

Attenuation

ADCL

ADCMUTE

Mute for Left and Right channel ADC:

0: Mute off

1: Mute on

WM8773 Datasheet(PDF) 23 Page - Wolfson Microelectronics plc

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