PC87334VLJ datasheet(10/102 Pages) NSC

10 / 102 page

10 Pin Description (Continued)

TABLE 1-1 Pin Descriptions (Alphabetical)

Symbol

PQFP

TQFP

Function

3F3RD

3F3 Read

This pin is used to implement the 3F3 Tape Drive Register (TDR) externally

3F3RD is active when read PIO from 3F3 hex address is active (A10 is not decoded) and

AEN e 0 This pin is configured when bit 1 of Function Control Register (FCR) is 1 (This

pin is shared with the IDEHI IRTX and DRID1 signals)

ADRATE01

98 48

96 46

Additional Data Rate 01

These outputs are similar to DRATE01 They are provided in

addition to DRATE01 They reflect the currently selected FDC data rate (bits 0 and 1 in

the Configuration Control Register (CCR) or the Data Rate Select Register (DSR)

whichever was written to last) ADRATE0 is configured when bit 0 of ASC is 1 ADRATE1

is configured when bit 4 of the Advanced SIO Configuration Register (ASC) is 1 (These

pins are shared with the IRQ5 and DENSEL signals)

A10–A0

21–31

19–29

Address

These microprocessor address lines determine which internal register is

accessed A0 – A10 are don’t cares during a DMA transfer

ACK

Acknowledge

This input is pulsed low by a connected printer to indicate that it has

received data from the parallel port This pin has a nominal 25 kX pull-up resistor attached

to it (This pin is shared with DR1 See Table 7-5 for further information)

AFD

Automatic Feed XT

When this signal is low the connected printer should automatically

line feed after each line is printed This pin is in a TRI-STATE condition 10 ns aftera0is

loaded into the corresponding Control Register bit The system should pull this pin high

using a 47 kX resistor (See DSTRB and Table 7-5 for further information)

AEN

Address Enable

This input disables function selection via A10 – A0 when it is high

Access during DMA transfer is NOT affected by this pin

ASTRB

Address Strobe

This signal is used in EPP mode as an address strobe It is active low

(See SLIN and Table 7-5 for further information)

BADDR01

55 58

53 56

Base Address

These bits determine one of four base addresses from which the Index

and Data Registers are offset (See Table 2-2) An internal pull-down resistor of 30 kX is

present on this pin Use a 10 kX resistor to pull this pin to VCC

BOUT12

73 65

71 63

BAUD Output

This multi-function pin provides the associated serial channel Baud Rate

generator output signal when test mode is selected in the Power and Test Configuration

function (See SOUT and CFG0 – 4 for further information)

BUSY

Busy

This pin is set high by the printer when it cannot accept another character It has a

nominal 25 kX pull-down resistor attached to it (See WAIT and Table 7-5 for further

information)

CFG0 – 4

65 66

63 64

Configuration on Power-up

These CMOS inputs select 1 of 32 default configurations in

which the PC87334VLJPC87334VJG powers-up (See Table 2-1) An internal pull-down

71 73

69 71

resistor of 30 kX is present on each pin Use a 10 kX resistor to pull these pins to VCC

CLK48

Clock 48

This pin is the CLK48 reset strap option During reset the value of this pin is

latched into bit 0 of TUP (CLK48 bit) A 30 kX internal pull-down resistor is present on this

pin Use a 10 kX resistor to pull it high during reset

CTS12

72 64

70 62

Clear to Send

When low this indicates that the MODEM or data set is ready to exchange

data The CTS signal is a MODEM status input whose condition the CPU can test by

reading bit 4 (CTS) of the MODEM Status Register (MSR) for the appropriate serial

channel Bit 4 is the complement of the CTS signal Bit 0 (DCTS) of the MSR indicates

whether the CTS input has changed state since the previous reading of the MSR CTS has

no effect on the transmitter

Note

Whenever the DCTS bit of the MSR is set an interrupt is generated if MODEM Status interrupts are enabled

D7–D0

10–17

8–15

I O

Data

Bi-directional data lines to the microprocessor D0 is the LSB and D7 is the MSB

These signals all have 24 mA (sink) buffered outputs

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