WM9705 datasheet(27/55 Pages) WOLFSON

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WM9705

Production Data

PD Rev 4.0 December 2003

AC-LINK AUDIO INPUT FRAME (SDATAIN)

SYNC

BITCLK

SDATAIN

CODEC

READY

SLOT(1)

SLOT(2)

SLOT(12)

'0'

TAG PHASE

DATA PHASE

20.8µS (48kHz)

12.288MHz

81.4nS

END OF PREVIOUS

AUDIO FRAME

TIME SLOT 'VALID' BITS

('1' = TIME SLOT CONTAINS

VALID PCM DATA)

SLOT (1)

SLOT (2)

SLOT (3)

SLOT (12)

Figure 14 AC-link Audio Input Frame

The audio input frame data streams correspond to the multiplexed bundles of all digital input data

targeting the AC’97 controller. As is the case for audio output frame, each AC-link audio input

frame consists of 12, 20-bit time slots.

Slot 0 is a special reserved time slot containing 16-bits, which are used for AC-link protocol

infrastructure.

Within slot 0 the first bit is a global bit (SDATAIN slot 0, bit 15) which flags whether the WM9705

is in the Codec Ready state or not. If the Codec Ready bit is a 0, this indicates that the WM9705

is not ready for normal operation. This condition is normal following the desertion of power on

reset for example, while the WM9705’s voltage references settle. When the AC-link Codec Ready

indicator bit is a 1, it indicates that the AC-link and the WM9705 control and status registers are in

a fully operational state. The AC’97 controller must further probe the Powerdown Control/Status

Prior to any attempts at putting the WM9705 into operation the AC’97 controller should poll the

first bit in the audio input frame (SDATAIN slot 0, bit 15) for an indication that the WM9705 has

gone Codec Ready.

Once the WM9705 is Codec Ready, then the next 12 bit positions sampled by the AC’97

controller indicate which of the corresponding 12 time slots are assigned to input data streams,

and that they contain valid data. Figure 14 illustrates the time slot based AC-link protocol.

There are several subsections within the WM9705 that can independently go busy/ready. It is the

responsibility of the WM9705 controller to probe more deeply into the WM9705 register file to

determine which of the WM9705 subsections are actually ready.

SYNC

BITCLK

SDATAIN

THE WM9705 SAMPLES SYNC ASSERTION HERE

AC'97 CONTROLLER SAMPLES FIRST

SDATAIN BIT OF FRAME HERE

END OF PREVIOUS AUDIO FRAME

CODEC

READY

SLOT (1)

SLOT (2)

Figure 15 Start of an Audio Input Frame

WM9705 Datasheet(PDF) 27 Page - Wolfson Microelectronics plc

WM9705 Datasheet(HTML) 27 Page - Wolfson Microelectronics plc

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