CTS9513API-2 datasheet(19/28 Pages) ETC

19 / 28 page

Celeritous Technical Services Corp

800.687.6510 / 806.793.0708

3308 34th St

FAX

806.793.0710

Lubbock, Texas 79410

http://www.celeritous.com

SPECIFICATIONS SUBJECT TO CHANGE WITHOUT NOTICE

Rev E

Tuesday, September 25,

CTS9513-2

5 Chan 16 bit 20MHz Counter/Timer

MODE K VARIABLE DUTY CYCLE RATE

GENERATOR WITH LEVEL GATING

Mode K is similar to Mode J with the exception that

the counter is enabled only after being ARMed and

when the selected Gate line is asserted. When the

Gate line is deasserted the counter stops. This allows

the gate to modulate the duty cycle of either state as

illustrated in Figure 20.

SOURCE

DATA

ARM COMMAND

GATE

COUNT VALUE

TC OUTPUT

TOGGLE OUTPUT

COUNTER MODE K WAVEFORMS

H-1

...

L-2

L-1

L-2

Figure 20 - CTS9513 Counter Mode K Representative Waveforms

SOURCE

DATA

ARM COMMAND

GATE

COUNT VALUE

TC OUTPUT

TOGGLE OUTPUT

COUNTER MODE L WAVEFORMS

...

L-2

L-1

H-1

...

L-1

L-2

L-3

Figure 21 - CTS9513 Counter Mode L Representative Waveforms

MODE L HARDWARE TRIGGERED

DELAYED PULSE ONE-SHOT

Mode L is used often as an externally triggered

delayed pulse generator, where the delay and pulse

width are both programmable. Like Modes J and K,

the counter cycles through the load count, reloads

from the hold at the first TC, and counts to the

second TC.

Unlike Modes J and K, however the counter is only

active after being ARMed and after a valid gate edge

is received. As shown in Figure 21 the gate edge

initiates one count cycle and is disregarded for the

rest of the cycle. After one count cycle (Load and

Hold) the counter stops until another gate edge is

received.

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