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CTS9513API-2 Datasheet(PDF) 25 Page - List of Unclassifed Manufacturers |
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CTS9513API-2 Datasheet(HTML) 25 Page - List of Unclassifed Manufacturers |
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25 / 28 page  Celeritous Technical Services Corp 800.687.6510 / 806.793.0708 3308 34th St FAX 806.793.0710 Lubbock, Texas 79410 http://www.celeritous.com SPECIFICATIONS SUBJECT TO CHANGE WITHOUT NOTICE Copyright 2000 Celeritous Technical Services Corp 25 Rev E Tuesday, September 25, CTS9513-2 5 Chan 16 bit 20MHz Counter/Timer NOTES 1. Any Input transition that occurs before this minimum setup requirement will be reflected in the contents read from the status register 2. Any Input transition that occurs before this minimum setup requirement will act on the counter before the execution of the operation initiated by the write and the counter may be off by one count 3. Any input transition that occurs after this minimum hold time is guaranteed to not influence the contents read from the status register on the current read operation 4. Any input transition that occurs after this minimum hold time is guaranteed to be seen by the counter as occurring after the action initiated by the write operation and the counter may be off by one count. 5. This parameter applies to cases where the write operation causes a change in the output bit. 6. The enabled count source is one of F1-F5, TCN-1 SRC1-SRC5 or GATE1-GATE 5, as selected in the applicable Counter Mode register. The timing diagram assumes the counter counts on rising source edges. The timing specifications are the same for falling-edge counting. 7. This parameter applies to edge gating (CM15-CM13=110 or 111) and gating when both CM7=1 and CM15-CM13?000. This parameter represents the minimum GATE pulse width needed to ensure that the pulse initiates counting or counter reloading. 8. This parameter applies to both edge and level gating (CM15- CM13=001 through 111 and CM7 =0). This parameter represents the minimum setup or hold times to ensure that the Gate input is seen at the intended level on the active source edge and the counter may be off by one count. 9. This parameter assumes that the GATENA input is unused (16-bit bus mode) or is tied high. In cases where the GATENA input is used, this timing specification must be met by both the GATE and GATENA inputs. 10. Signals F1-F5 cannot be directly monitored by the user. The phase difference between these signals will manifest itself by causing counters using two different F signals to count at different times on nominally simultaneous transitions in the F signals. F1=X2. 11. This timing specification assumes that CS is active whenever RD or WR are active. CS may be held active indefinitely. 12. This parameter assumes X2 is driven from an external gate with a square wave. 13. This parameter assumes that the write operation is to the command register. 14. This timing specification applies to single-action commands only (e.g. LOAD, ARM, SAVE, etc.) For double action commands such as LOAD AND ARM and DISARM AND SAVE, TWHEH minimum = 700ns. 15. In short data write mode, TWHRL and TWHWL minimum = 1000 ns. 16. This parameter applies to the hardware retrigger/save modes N, O, Q, R, and X (CM7 = 1 and CM15-CM13<>000). This parameter ensures that the gating pulse initiates a hardware retrigger/save operation. 17. This parameter applies to hardware load source select modes S and V (CM7 = 1 and CM15-CM13=000). This parameter represents the minimum hold time to ensure that the GATE input selects the correct load source on the active source edge. Param Description Figure Min Typ Max Tavrl C/D Valid to Read Low 2 15 Tavwh C/D Valid to Write High 2 30 Tdvwh Data In Valid to Write High 2 40 Tehrl Count Source High to Read (setup time) Note 2,7 2 100 Tehwh Count Source High to Write High (setup time) Note 3,7 2 50 Tgvwh Gate valid to Write High Note 3,10 2 0 Trhax Read High to C/D don't Care 2 0 Trheh Read High to Count Source High Note 4,7 2 0 Trhqx Read High to Data Out Invalid 2 20 Trhqz Read High to Data Out Hi-Z (Bus Release Time) 2 40 Trhrl Read High to Read Low (Read Recovery Time) 2 500 Trhsh Read High to CS High Note 12 2 0 Trhwl Read High to Write Low (Read Recovery Time) 2 500 Trlqv Read Low to Data Out Valid 2 50 Trlqx Read Low to Data Bus Driven (Bus Drive Time) 2 20 Trlrh Read Low to Read High (Read Pulse Duration) Note 12 2 80 Tslrl CS Low to Read Low Note 12 2 10 Tslwh CS Low to Write High Note 12 2 80 Twhax Write High to C/D Don't Care 2 0 Twhdx Write High to Data In Don't Care 2 0 Twheh Write High to Count Source High Note 5, 7, 14, 15 2 200 Twhgv Write High to Gate valid Note 5, 10, 14 2 200 Twhrl Write High to Read Low (Write Recovery Time) Note 16 2 500 Twhsh Write High to CS High Note 12 2 0 Twhwl Write High to Write Low (Write Recovery Time) Note 16 2 500 Twhyv Write High to Out Valid Note 6, 14 2 300 Twlwh Write Low to Write High (Write Pulse Duration) Note 12 2 75 Table 14 - Bus Timing Specifications |
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