CTS9513API-2 datasheet(10/28 Pages) ETC

10 / 28 page

Celeritous Technical Services Corp

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SPECIFICATIONS SUBJECT TO CHANGE WITHOUT NOTICE

Rev E

Tuesday, September 25,

CTS9513-2

5 Chan 16 bit 20MHz Counter/Timer

CMP2

CMP1

OUT5

OUT4

OUT3

OUT2

OUT1

Comparator

Counter Output Status

Byte

Reflects actual state of

Interrupt Output

Pointer

Reflects Actual State of Output

Table 7 - Status Register

a Write pulse. Repetitive waveforms do not show the

write pulse or ARM command. The letters L and H

are used in the figures to denote Load and Hold

arbitrary counter values.

In all cases, the counter begins counting on the first

count source edge following the Write pulse in

software triggered modes and the first source edge

following a valid gate edge in hardware triggered or

enabled modes.

In gate controlled modes which inhibit counting, the

counter is suspended for any valid source edges that

occur after de-assertion of the gate line.

CTS9513AXI-2 ERRATA

Although tested extensively to ensure full compliance

with the original AM9513Axx device functions and

operating modes, several functional anomalies have

come to our attention. Both current and potential

users of this device should take note of these.

Devices Affected:

All 1996, 97, 98, 99 and 2000 devices manufactured

to date

Planned Action:

There are no immediate plans to correct these

defects until further testing can be completed to

detect any further anomalies.

Work-Arounds:

There is no current work-around for these problems

for existing designs.

CRYSTAL OSCILLATOR

The CTS9513 does not incorporate a crystal oscilla-

tor and must be driven from an external TTL compati-

ble oscillator source.

COMMAND DATA READ/WRITE DATA

LATCH

In this implementation of the 9513 data being written

to the device is not latched on the rising (trailing)

edge of the write strobe. Data in this device is latched

into the command and control registers on the low

level of the write strobe. This means that the data

must be stable up until shortly before the rising edge

of the write strobe. This appears to be an artifact of

the way the 8 bit sequential write mode was

implemented in order to correctly increment the byte

pointer and latch the data on the one write strobe.

To date we have only seen this create a problem in

one

instance

ISA

bus

Counter/Timer

instrumentation card where the ISA bus decoding

was incorrectly implemented. In that instance, a delay

in de-asserting the chip select was causing the

leading edge of a write strobe for another I/O device

to appear prior to the trailing edge of the Chip Select

signal. This was interpreted as another valid write to

the 9513 device causing invalid data to be written to

the device.

MM15

MM14

MM13

MM12

MM11

MM10

MM9

MM8

MM7

MM6

MM5

MM4

MM3

MM2

MM1

MM0

SCALE

POINT

BUS

FGATE1

DIV1-8

DIV1-4

DIV1-2

DIV1-1

FOUT1-8 FOUT1-4 FOUT1-2 FOUT1-1

COMP2

COMP1

TOD2

TOD1

Scale

Data

Data Bus FOUT

FOUT Divider

FOUT Source Select

Comparator

Time of Day Mode

Mode

Pointer

Width

Mode

0 BIN

0 Enable 0 = 8

0 = On

0000 = Divide by 16

0000 = F1

00 = Disabled

00 = TOD Disabled

1 BCD

1 Disable 1 = 16

1 = Off

0001 = Divide by 1

001 = Source 1

01 = Comparator 1 On 01 = TOD Enabled /5

0010 = Divide by 2

0010 = Source 2

10 = Comparator 2 On 10 = TOD Enabled /6

0011 = Divide by 3

0011 = Source 3

11 = Both On

11 = TOD Enabled /10

0100 = Divide by 4

0100 = Source 4

0101 = Divide by 5

0101 = Source 5

0110 = Gate 1

0111 = Gate 2

1000 = Gate 3

1001 = Gate 4

1010 = Gate 5

1011 = F1

1100 = F2

1101 = F3

1110 = F4

1111 = Divide by 16

1111 = F5

Table 8 - Master and Auxiliary Master Mode Register Definitions

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