| Electronic Components Datasheet Search |
|
CTS9513API-2 Datasheet(PDF) 12 Page - List of Unclassifed Manufacturers |
|
|
|||||||||||||||||||||||||||||
CTS9513API-2 Datasheet(HTML) 12 Page - List of Unclassifed Manufacturers |
|
12 / 28 page ![]() Celeritous Technical Services Corp 800.687.6510 / 806.793.0708 3308 34th St FAX 806.793.0710 Lubbock, Texas 79410 http://www.celeritous.com SPECIFICATIONS SUBJECT TO CHANGE WITHOUT NOTICE Copyright 2000 Celeritous Technical Services Corp 12 Rev E Tuesday, September 25, CTS9513-2 5 Chan 16 bit 20MHz Counter/Timer Figure 9 - CTS9513 Counter Gating Input Logic Block Diagram MODE V (FSK) ERROR An error in implementing the special gate function prevents the implementation of Mode V (FSK Generator). The gate level is supposed to control whether the counter is reloaded from the LOAD or HOLD register to determine the output rate generator frequency and allow switching between two frequencies to produce Frequency Shift Keying (FSK) modulation. When programmed for Mode V, the current device Revision will reload only from the HOLD register regardless of the state of the GATE input. This appears to be a general problem with the “special gate” function that controls reloading of the counter from the Load or Hold register depending on the state of the gate. MODE J ERROR The counters will not allow a count of 1 to be set in the load and/or hold registers COUNTER SAVE ERRORS Due to the asynchronous nature of this part (and to an extent the original AMD AM9513) we have seen errors in the saved counter data when a counter save command is issued. This occurs when the write strobe rising edge for a save command occurs simul- taneously with a counter clock edge and the counter tries to save the current count while also trying to in- crement or decrement the counter. The only solid solution we have found for this proble is for the bus clock to also be the master clock or to be phased locked to it in order for the timing of bus read/write cycles to be deterministic with respect to the counter clock edges. Figure 8 - CTS9513 Counter Internal Prescaler Block Diagram 4 BITS 4 BITS 4 BITS 4 BITS F1 F2 F3 F4 F5 CLK IN FREQUENCY BCD SCALING BINARY SCALING F1 F2 F3 F4 F5 CLK IN CLK IN CLK / 16 CLK / 256 CLK / 4096 CLK / 65536 CLK / 10 CLK / 100 CLK / 1000 CLK / 10000 COUNTER MODE REGISTER GATE INPUT MUX AND POLARITY SELECT TC-1 GATE -1 GATE GATE+1 GATE EN EDGE AND LEVEL GATE CONTROL COUNTER |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |