ISL6569ACR datasheet(7/22 Pages) RENESAS

7 / 22 page

ISL6569A

FN9092 Rev 2.00

Page 7 of 22

Dec 29, 2004

Functional Pin Description

GND

Bias and reference ground for the IC.

OVP

Over-voltage protection pin. This pin is pulled to VCC and is

latched when an over-voltage condition is detected. Connect

this pin to the gate of an SCR or MOSFET tied across VIN

and ground. A fuse must be placed upstream to open the

input supply rail and prevent damage to the load device.

VID4, VID3, VID2, VID1, VID0

The state of these five inputs program the internal DAC,

which provides the reference voltage for output regulation.

Connect these pins to either open-drain or active pull-up

type outputs. Pulling these pins above 2.9V can cause a

reference offset inaccuracy.

OFS

Connecting a resistor between this pin and ground creates a

positive offset voltage which is added to the DAC voltage,

allowing easy implementation of load-line regulation. For no

offset, simply tie this pin to ground.

FB and COMP

The internal error amplifier inverting input and output

respectively. Connect the external R-C feedback

compensation network of the regulator to these pins.

IOUT

The current carried out of this pin is proportional to output

current and can be used to incorporate output voltage droop

and/or load sharing. The scale factor is set by the ratio of the

ISEN resistors and the lower MOSFET rDS(ON). If droop is

desired, connect this pin to FB. When not used for droop or

load sharing, simply leave this pin open.

VSEN, RGND, VDIFF

VSEN and RGND are the inputs to the differential remote-

sense amplifier. Connect these pins to the sense points of

the remote load. Connect an appropriately sized feedback

resistor, RFB, between VDIFF and FB.

VCC

Supplies all the power necessary to operate the chip. The IC

starts to operate when the voltage on this pin exceeds the

rising POR threshold and shuts down when the voltage on

this pin drops below the falling POR threshold. Connect this

pin directly to a +5V supply or through a series 255

 resistor

to a +12V supply.

ISEN1, ISEN2

Current sense inputs. A resistor connected between these

pins and their respective phase nodes sets a current

proportional to the current in the lower MOSFET during it’s

conduction interval. This current is used as a reference for

channel balancing, load sharing, protection, and load-line

droop.

PWM1, PWM2

Pulse-width modulating outputs. Connect these pins to the

individual HIP660x driver PWM input pins. These logic

outputs command the driver IC(s) in switching the half-

bridge configuration of MOSFETs.

PGOOD

Power good is an open-drain logic output that changes to a

logic low when the voltage at VDIFF is 350mV below the VID

setting or above 2.2V.

FS/DIS

A dual function pin for setting the switching frequency and

disabling the controller. Place a resistor from this pin to

ground to set the switching frequency between 25kHz and

1MHz. Pulling this pin below 0.8V disables the controller.

Threshold sensitive enable input of the controller. Transition

this pin above 1.23V (typical enable threshold) to initiate a

soft-start cycle. Pull this pin below 1.14V, taking into account

the enable hysteresis, to disable the controller once in

operation. Connect a resistor divider to this pin to set the

power-on voltage level for proper coordination with Intersil

MOSFET drivers. If this function is not required, simply tie

this pin to VCC.

Multi-Phase Control

Microprocessor load current profiles have increased to the

point where the multi-phase power conversion advantage is

pronounced. The technical challenges associated with

producing a single-phase converter which is both cost-

effective and thermally viable have forced a change to the

cost-saving approach of multi-phase. The ISL6569A

controller helps reduce the complexity of implementation by

integrating vital functions and requiring minimal output

components. The block diagram in Figure 1 provides a top

level view of multi-phase power conversion using the

ISL6569A controller.

ISL6569ACR

32 LEAD QFN 5x5

ISL6569ACB

24 LD SOIC

GND

OVP

VID4

VID3

VID2

OFS

VCC

ISEN1

VSEN

PWM2

GND

COMP

RGND

VID0

PWM1

VID1

ISEN2

GND

IOUT

VDIFF

PGOOD

FS/DIS

VID2

VID1

VID0

OFS

COMP

ISEN2

GND

PWM2

PWM1

ISEN1

GND

BOTTOM

SIDE PAD

ISL6569ACR Datasheet(PDF) 7 Page - Renesas Technology Corp

ISL6569ACR Datasheet(HTML) 7 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22

Datasheet Download

Link URL