ISL6569ACR datasheet(13/22 Pages) RENESAS

13 / 22 page

ISL6569A

FN9092 Rev 2.00

Page 13 of 22

Dec 29, 2004

Operation Initialization

Before converter operation is initialized, proper conditions

must exist on the enable and disable inputs. Once these

conditions are met, the controller begins a soft-start interval.

Once the output voltage is within the proper window of

operation, the PGOOD output changes state to update an

external system monitor.

Enable and Disable

The PWM outputs are held in a high-impedance state to

assure the drivers remain off while in shutdown mode. Four

separate input conditions must be met before the ISL6569A

is released from shutdown mode.

First, the bias voltage applied at VCC must reach the internal

power-on reset (POR) circuit rising threshold. Once this

threshold is met, the EN input signal becomes the gate for

soft-start initialization. Hysteresis between the rising and

falling thresholds insures that once enabled, the ISL6569A

will not inadvertently turn off unless the bias voltage drops

substantially. See Electrical Specifications for specifics on

POR rising and falling thresholds.

Second, the ISL6569A features an enable input (EN) for

power sequencing between the controller bias voltage and

another voltage rail. The enable comparator holds the

ISL6569A in shutdown until the voltage at EN rises above

1.23V. The enable comparator has about 90mV of

hysteresis to prevent bounce. It is important that the driver

ICs reach their POR level before the ISL6569A becomes

enabled. The schematic in Figure 8 demonstrates

sequencing the ISL6569A with the HIP660X family of Intersil

MOSFET drivers which require 12V bias.

Third, the frequency select/disable input (FS/DIS) will

shutdown the converter when pulled to ground. Under this

condition, the internal oscillator is disabled. The oscillator

resumes operation upon release of FS/DIS and a soft-start

sequence is initiated.

Finally, the 11111 VID code is reserved as a signal to the

controller that no load is present. The controller will enter

shutdown mode after receiving this code and will start up

upon receiving any other code.

To enable the controller, VCC must be greater than the POR

threshold; the voltage on EN must be greater than 1.23V;

FS/DIS must not be grounded; and VID cannot be equal to

11111. Once these conditions are true, the controller

immediately initiates a soft-start sequence.

Soft-Start

The soft-start time, tSS, is determined by an 11-bit counter

that increments with every pulse of the phase clock. For

example, a converter switching at 250kHz per phase has a

soft-start time of

During the soft-start interval, the soft-start voltage, VRAMP,

increases linearly from zero to 140% of the programmed

DAC voltage. At the same time a current source, IRAMP, is

decreasing from 160

A down to zero. These signals are

connected as shown in Figure 9 (IOUT may or may not be

connected to FB depending on the particular application).

The ideal diodes in Figure 9 assure that the controller tries to

regulate its output to the lower of either the reference voltage

or VRAMP. Since IRAMP creates an initial offset across RFB

(RFB x 160A), the first PWM pulse will not be seen until

VRAMP is greater than the RFBIRAMP offset. This produces a

delay after the ISL6569A enables before the output voltage

starts moving. For example, if VID = 1.5V, RFB = 1k and

TSS = 8.3ms, the delay time can be expressed using

Equation 10.

FIGURE 8. POWER SEQUENCING USING THRESHOLD-

SENSITIVE ENABLE (EN) FUNCTION

1.23V (± 2%)

EXTERNAL CIRCUIT

ISL6569A INTERNAL CIRCUIT

+12V

VCC

+5V

POR

CIRCUIT

OV LATCH

SIGNAL

10.7k



1.40k



ENABLE

COMPARATOR

TSS

2048

fSW

-------------8.3ms

(EQ. 9)

FIGURE 9. RAMP CURRENT AND VOLTAGE FOR

REGULATING SOFT-START SLOPE

AND DURATION

IAVG

REFERENCE

EXTERNAL CIRCUIT

ISL6569A INTERNAL CIRCUIT

COMP

RFB

IOUT

VDIFF

ERROR AMPLIFIER

VOLTAGE

VCOMP

VRAMP

IRAMP

IDEAL DIODES

tDELAY

TSS

1.4 VID



RFB160 10 6

–



-----------------------------------------

---------------------------------------------------

560

s

(EQ. 10)

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