ISL6569ACR datasheet(10/22 Pages) RENESAS

10 / 22 page

ISL6569A

FN9092 Rev 2.00

Page 10 of 22

Dec 29, 2004

Current Sensing

During the forced off time following a PWM transition low, the

controller senses channel load current by sampling the voltage

across the lower MOSFET rDS(ON). A ground-referenced

amplifier, internal to the ISL6569A, connects to the PHASE

node through a resistor, RISEN. The voltage across RISEN is

equivalent to the voltage drop across the rDS(ON) of the lower

MOSFET while it is conducting. The resulting current into the

ISEN pin is proportional to the channel current, IL. The ISEN

current is then sampled and held after sufficient settling time

every switching cycle. The sampled current is used for channel-

current balance, load-line regulation, overcurrent protection,

and module current sharing.

The circuitry shown in Figure 4 represents channel-1 of a

two channel converter. This circuitry is repeated for

channel-2 of the converter. From Figure 4, the following

equation for channel-1 sampled current, I1, is derived

where IL1 is half of the total load current.

If rDS(ON) sensing is not desired, an independent current-

sense resistor in series with the lower MOSFET source can

serve as a sense element.

Channel-Current Balance

The sampled current from both channels, I1 and I2, is used

to gauge both overall load current and the relative channel

current carried in each leg of the converter. The individual

sample currents are averaged. The resulting average

current, IAVG, provides a measure of the total load current

demand on the converter and the appropriate level of

channel current. Using Figures 4 and 6, the average current

is defined as:

where IOUT is the total load current.

The average current is then subtracted from the individual

channel sample currents. The resulting error current, IER, is

then filtered before it adjusts VCOMP. The modified VCOMP

signal is compared to a sawtooth ramp signal and produces

a pulse width which corrects for any unbalance and drives

the error current toward zero. Figure 6 illustrates Intersil’s

patented current balance method as implemented on one

channel of a multi-phase converter.

Two considerations designers face are MOSFET selection

and inductor design. Both are significantly improved when

channel currents track at any load level. The need for

complex drive schemes for multiple MOSFETs, exotic

magnetic materials, and expensive heat sinks is avoided.

Resulting in a cost-effective and easy to implement solution

relative to single-phase conversion. Channel current balance

insures the thermal advantage of multi-phase conversion is

realized. Heat dissipation is spread over multiple channels

and a greater area than single phase approaches.

In some circumstances, it may be necessary to deliberately

design some channel-current unbalance into the system. In

a highly compact design, one channel may be able to cool

more effectively than the other due to nearby air flow or heat

sinking components. The other channel may have more

difficulty cooling with comparatively less air flow and heat

sinking. The hotter channel may also be located close to

other heat-generating components tending to drive it’s

temperature even higher. In these cases, the proper

selection of the current sense resistors (RISEN in Figure 4)

introduces channel current unbalance into the system.

Increasing the value of RISEN in the cooler channel and

decreasing it in the hotter channel moves both channels into

thermal balance at the expense of current balance.

FIGURE 4. CHANNEL 1 INTERNAL AND EXTERNAL

CURRENT-SENSING CIRCUITRY

I1 I

SEN

IL1

rDS ON



RISEN

--------------------------

ISEN1

RISEN

SAMPLE

HOLD

ISL6569A INTERNAL CIRCUIT

EXTERNAL CIRCUIT

VIN

CHANNEL 1

UPPER MOSFET

CHANNEL 1

LOWER MOSFET

IL1 rDS ON



IL1

SAMPLED

CURRENT

IL1

rDS ON



RISEN

----------------------

(EQ. 3)

IAVG

I1 I2

----------------

IAVG

IOUT

-------------

rDS ON



RISEN

----------------------

(EQ. 4)

FIGURE 5. CHANNEL-1 PWM FUNCTION AND CURRENT-

BALANCE ADJUSTMENT

2

IAVG



f(j

)

PWM1

VCOMP

SAWTOOTH SIGNAL

IER

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