ISL6569ACR datasheet(14/22 Pages) RENESAS

14 / 22 page

ISL6569A

FN9092 Rev 2.00

Page 14 of 22

Dec 29, 2004

Following the delay, the soft start ramps linearly until VRAMP

reaches VID. For the system described above, this first

linear ramp will continue for approximately

The final portion of the soft-start sequence is the time

remaining after VRAMP reaches VID and before IRAMP gets to

zero. This is also characterized by a slight change in the slope

of the output voltage ramp which, for the current example,

exists for a time of

This behavior is seen in the example in Figure 10 of a converter

switching at 500kHz. For this converter, RFB is set to 2.67k

leading to TSS = 4.0ms, tDELAY = 700ns, tRAMP1 = 2.23ms,

and tRAMP2 = 1.17ms.

NOTE: Switching frequency 500kHz and RFB = 2.67k

Fault Monitoring and Protection

The ISL6569A actively monitors voltage and current

feedback to detect fault conditions. Fault monitors trigger

protective measures to prevent damage to a microprocessor

load. One common power good indication signal is provided

for linking to external system monitors. The schematic in

Figure 11 outlines the interaction between the fault monitors

and the power good signal.

Power Good Signal

The power good pin (PGOOD) is an open-drain logic output

which indicates that the converter is operating properly and

the output voltage is within a set window. The under-voltage

(UV) and over-voltage (OV) comparators create the output

voltage window. The controller also takes advantage of

current feedback to detect output over-current (OC)

conditions. PGOOD pulls low during shutdown and releases

high during soft-start once the output voltage exceeds the

UV threshold. Once high, PGOOD will only transition low

when the controller is disabled or a fault condition is

detected. It will return high under certain circumstances once

a fault clears.

Under-Voltage Protection

The voltage on VDIFF is internally offset by 350mV before it

is compared with the DAC reference voltage. By positively

offsetting the output voltage, an UV threshold is created

which moves relative to the VID code. During soft-start, the

slow rising output voltage eventually exceeds the UV

threshold. Assuming the POR leg of the PGOOD NOR gate

has not detected an OC fault, the PGOOD signal will go

high.

If a fault condition arises during operation and the output

voltage drops below the UV threshold, PGOOD will

immediately pull low, but converter operation will continue.

PGOOD will return high once the output voltage surpasses

the UV threshold.

If the ISL6569A is disabled during operation, the PGOOD

signal will not pull low until the output voltage decays below

the UV threshold.

Over-Voltage Protection

When the output of the differential amplifier (VDIFF) reaches

2.2V, PGOOD immediately goes low indicating a fault. Two

protective actions are taken by the ISL6569A to protect the

microprocessor load.

First, all PWM outputs are commanded low. Directing the

Intersil drivers to turn on the lower MOSFETs; shunting the

output to ground preventing any further increase in output

voltage. The PWM outputs remain low until VDIFF falls to the

programmed DAC level at which time they go into a high-

tRAMP1

TSS

1.4

-----------

tDELAY

–

5.27ms

(EQ. 11)

tRAMP2

TSS tRAMP1

–

tDELAY

–

2.34ms

(EQ. 12)

FIGURE 10. SOFT-START WAVEFORMS FOR ISL6569A

BASED MULTI-PHASE BUCK CONVERTER

1ms/div

EN, 5V/DIV

VOUT, 500mV/DIV

tDELAY tRAMP1

tRAMP2

FIGURE 11. POWER GOOD AND PROTECTION CIRCUITRY

OVP

POR

CIRCUIT

2.2V

VDIFF

A

IAVG

DAC

REFERENCE

350mV

PGOOD

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