MPC9331 datasheet(5/12 Pages) MOTOROLA

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Advanced Clock Drivers Devices

Freescale Semiconductor

MPC9331

Table 7. AC Characteristics (VCC = 3.3V ± 5%, TA = 0°C to 70°C)(1)

1. AC characteristics apply for parallel output termination of 50

Ω to VTT.

Symbol

Characteristics

Min

Typ

Max

Unit

Condition

fREF

Input reference frequency

÷2 feedback

PLL mode, external feedback

÷4 feedback

÷6 feedback

÷8 feedback

÷12 feedback

PLL mode, internal feedback

(

÷8 feedback)

Input reference frequency in PLL bypass mode(2)

2. In bypass mode, the MPC9331 divides the input reference clock.

100.0

50.0

33.3

25.0

16.67

25.0

240.0

120.0

80.0

60.0

40.0

60.0

240

MHz

PLL locked

fVCO

VCO lock frequency range(3)

3. The input frequency fREF must match the VCO frequency range divided by the feedback divider ratio FB: fREF = fVCO ÷ FB.

200

480

MHz

fMAX

Output Frequency

÷2 output

÷4 output

÷6 output

÷8 output

÷12 output

100.0

50.0

33.3

25.0

16.67

240.0

120.0

80.0

60.0

40.0

MHz

PLL locked

VPP

Peak-to-peak input voltage

PCLK, PCLK

400

1000

LVPECL

VCMR

(4)

4. VCMR (AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the VCMR range

and the input swing lies within the VPP (AC) specification. Violation of VCMR or VPP impacts static phase offset t(∅).

Common Mode Range

PCLK, PCLK

1.2

VCC – 0.9

LVPECL

tPW,MIN

Input Reference Pulse Width(5)

5. Calculation of reference duty cycle limits: DCREF,MIN = tPW,MIN ⋅ fREF ⋅ 100% and DCREF,MAX = 100% – DCREF,MIN.

2.0

tR, tF

CCLK Input Rise/Fall Time(6)

6. The MPC9331 will operate with input rise/fall times up to 3.0 ns, but the AC characteristics, specifically t(∅), tPW,MIN, DC and fMAX can only

be guaranteed if tR, tF are within the specified range.

1.0

0.8 to 2.0 V

t(∅)

Propagation Delay

CCLK to FB_IN(7)

(static phase offset)

PCLK to FB_IN(7)

CCLK or PCLK to FB_IN(8)

7. Data valid for fREF = 50 MHz and a PLL feedback of ÷8 (e.g. QAx connected to FB_IN and FSELA=1, PWR_DN=1).

8. Data valid for 16.67 MHz < fREF < 100 MHz and any feedback divider. tsk(O) [s] = tsk(O) [°] ÷ (fREF ⋅ 360°).

–250

–180

–3.0

–130

–30

–50

+120

+3.0

FB_SEL = 1

and PLL locked

tsk(O)

Output-to-output Skew

150

Output duty cycle(9)

9. Output duty cycle is DC = (0.5

± 500 ps ⋅ fOUT) ⋅ 100%. (e.g. the DC range at fOUT = 100 MHz is 45% < DC < 55%).

÷2)–500

÷2

÷2)+500

tR, tF

Output Rise/Fall Time

0.1

1.0

0.55 to 2.4 V

tPLZ, HZ

Output Disable Time

8.0

tPZL, LZ

Output Enable Time

tJIT(CC)

Cycle-to-cycle jitter(10)

10. All outputs in

÷4 divider configuration.

200

tJIT(PER)

Period Jitter

125

tJIT(∅)

I/O Phase Jitter

RMS (1

σ)

PLL closed loop bandwidth(11)

÷ 4 feedback

PLL mode, external feedback

÷ 6 feedback

÷ 8 feedback

÷12 feedback

11. –3 dB point of PLL transfer characteristics.

2.0–8.0

1.2–4.0

1.0–3.0

0.7–2.0

MHz

tLOCK

Maximum PLL Lock Time

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