Advanced Clock Drivers Devices

10

Freescale Semiconductor

MPC9331

Test Reference

Figure 10. Output Duty Cycle (DC)

Figure 11. I/O Jitter

CCLK

FB_IN

in a random sample of cycles

GND

GND

CCLK

FB_IN

The pin-to-pin skew is defined as the worst case difference

in propagation delay between any similar delay path within a

single device

GND

GND

The time from the PLL controlled edge to the non controlled

edge, divided by the time between PLL controlled edges,

expressed as a percentage

GND

Figure 12. Cycle-to-Cycle Jitter

Figure 13. Period Jitter

Figure 14. Output Transition Time Test Reference

2.4

0.55

The variation in cycle time of a signal between adjacent cycles,

over a random sample of adjacent cycle pairs

The deviation in cycle time of a signal with respect to the ideal

period over a random sample of cycles