Advanced Clock Drivers Devices

8

Freescale Semiconductor

MPC9331

APPLICATIONS INFORMATION

Power Supply Filtering

The MPC9331 is a mixed analog/digital product. Its analog

circuitry is naturally susceptible to random noise, especially if

this noise is seen on the power supply pins. Random noise

characteristics, for instance, I/O jitter. The MPC9331 provides

this design technique is to isolate the high switching noise

digital outputs from the relatively sensitive internal analog

phase-locked loop. In a digital system environment where it

is more difficult to minimize noise on the power supplies, a

second level of isolation may be required. The simple but

effective form of isolation is a power supply filter on the

power supply filter scheme. The MPC9331 frequency and

phase stability is most susceptible to noise with spectral

content in the 100 kHz to 20 MHz range. Therefore the filter

should be designed to target this range. The key parameter

that needs to be met in the final filter design is the DC voltage

pin) is typically 8 mA (12 mA maximum), assuming that a

defined by the required filter characteristics: the RC filter

should provide an attenuation greater than 40 dB for noise

whose spectral content is above 100 kHz. In the example RC

filter shown in Figure 3, the filter cut-off frequency is around

3-5 kHz and the noise attenuation at 100 kHz is better than

42 dB.

As the noise frequency crosses the series resonant point

of an individual capacitor its overall impedance begins to look

inductive and thus increases with increasing frequency. The

parallel capacitor combination shown ensures that a low

impedance path to ground exists for frequencies well above

the bandwidth of the PLL. Although the MPC9331 has

several design features to minimize the susceptibility to

power supply noise (isolated power and grounds and fully

differential PLL) there still may be applications in which

overall performance is being degraded due to system power

supply noise. The power supply filter schemes discussed in

this section should be adequate to eliminate power supply

noise related problems in most designs.

Driving Transmission Lines

The MPC9331 clock driver was designed to drive high-

speed signals in a terminated transmission line environment.

To provide the optimum flexibility to the user, the output

drivers were designed to exhibit the lowest impedance

possible. With an output impedance of less than 20

Ω, the

drivers can drive either parallel or series terminated

transmission lines. For more information on transmission

lines, the reader is referred to Freescale application note

AN1091. In most high performance clock networks,

point-to-point distribution of signals is the method of choice.

In a point-to-point scheme, either series terminated or parallel

terminated transmission lines can be used. The parallel

technique terminates the signal at the end of the line with a

50

This technique draws a fairly high level of DC current and

thus only a single terminated line can be driven by each

output of the MPC9331 clock driver. For the series terminated

case, however, there is no DC current draw, thus the outputs

can drive multiple series terminated lines. Figure 4 illustrates

an output driving a single series terminated line versus two

series terminated lines in parallel. When taken to its extreme

the fanout of the MPC9331 clock driver is effectively doubled

due to its capability to drive multiple lines.

Figure 4. Single versus Dual Transmission Lines

The waveform plots in Figure 5 show the simulation results

of an output driving a single line versus two lines. In both

cases, the drive capability of the MPC9331 output buffer is

more than sufficient to drive 50

Ω transmission lines on the

incident edge. Note from the delay measurements in the

simulations, a delta of only 43 ps exists between the two

differently loaded outputs. This suggests that the dual line

driving need not be used exclusively to maintain the tight

output-to-output skew of the MPC9331. The output waveform

in Figure 5 shows a step in the waveform; this step is caused

by the impedance mismatch seen looking into the driver. The

parallel combination of the 36

Ω series resistor plus the

output impedance does not match the parallel combination of

the line impedances. The voltage wave launched down the

two lines will equal:

MPC9331

10 nF

33...100 nF

14

Ω

IN

MPC9331

OUTPUT

BUFFER

OutA

14

Ω

IN

MPC9331

OUTPUT

BUFFER

OutB0

OutB1