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5X1503 Datasheet(PDF) 21 Page - Integrated Device Technology |
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5X1503 Datasheet(HTML) 21 Page - Integrated Device Technology |
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21 / 28 page  21 ©2019 Integrated Device Technology, Inc June 19, 2019 5X1503 Datasheet Byte 10: PLL Period Control Byte 11: PLL M Divider Setting (Apply to 5X1503S) Byte 11: PLL M Divider Setting (Apply to 5X1503/5X1503L) Byte 0Ah Name Control Function Type 0 1 PWD Bit 7 PLL_PERIOD[7] PLL period control bit 7 R/W — — 0 Bit 6 PLL_PERIOD[6] PLL period control bit 6 R/W — — 0 Bit 5 PLL_PERIOD[5] PLL period control bit 5 R/W — — 0 Bit 4 PLL_PERIOD[4] PLL period control bit 4 R/W — — 0 Bit 3 PLL_PERIOD[3] PLL period control bit 3 R/W — — 0 Bit 2 PLL_PERIOD[2] PLL period control bit 2 R/W — — 0 Bit 1 PLL_PERIOD[1] PLL period control bit 1 R/W — — 0 Bit 0 PLL_PERIOD[0] PLL period control bit 0 R/W — — 0 Byte 0Bh Name Control Function Type 0 1 PWD Bit 7 PLL_MDIV1 PLL reference divider 1 R/W disable M DIV1 bypadd divider (/1) 1 Bit 6 PLL_MDIV2 PLL reference divider 2 R/W disable M DIV2 bypadd divider (/2) 0 Bit 5 PLL_MDIV[5] PLL reference divider control bit 5 R/W 3–63, default is 26 0 Bit 4 PLL_MDIV[4] PLL reference divider control bit 4 R/W 1 Bit 3 PLL_MDIV[3] PLL reference divider control bit 3 R/W 1 Bit 2 PLL_MDIV[2] PLL reference divider control bit 2 R/W 0 Bit 1 PLL_MDIV[1] PLL reference divider control bit 1 R/W 1 Bit 0 PLL_MDIV[0] PLL reference divider control bit 0 R/W 0 Byte 0Bh Name Control Function Type 0 1 PWD Bit 7 PLL_MDIV1 PLL reference divider 1 R/W disable M DIV1 bypadd divider (/1) 0 Bit 6 PLL_MDIV2 PLL reference divider 2 R/W disable M DIV2 bypadd divider (/2) 0 Bit 5 PLL_MDIV[5] PLL reference divider control bit 5 R/W 3–63, default is 26 0 Bit 4 PLL_MDIV[4] PLL reference divider control bit 4 R/W 1 Bit 3 PLL_MDIV[3] PLL reference divider control bit 3 R/W 1 Bit 2 PLL_MDIV[2] PLL reference divider control bit 2 R/W 0 Bit 1 PLL_MDIV[1] PLL reference divider control bit 1 R/W 1 Bit 0 PLL_MDIV[0] PLL reference divider control bit 0 R/W 0 |
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