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5X1503 Datasheet(PDF) 24 Page - Integrated Device Technology |
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5X1503 Datasheet(HTML) 24 Page - Integrated Device Technology |
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24 / 28 page ![]() 24 ©2019 Integrated Device Technology, Inc June 19, 2019 5X1503 Datasheet Byte 15: Output Divider 2 Control Byte 16: PLL Operation Control Register Byte 17: OE and DFC Control Byte 0Fh Name Control Function Type 0 1 PWD Bit 7 OUTDIV2[4] Output divider2 control bit 4 R/W DIV1[3:2] = 1, 3, 5, 7, 9, 11; DIV1[1:0] = 1, 2, 4, 8; DefaultDivider=00001=3 0 Bit 6 OUTDIV2[3] Output divider2 control bit 3 R/W 0 Bit 5 OUTDIV2[2] Output divider2 control bit 2 R/W 0 Bit 4 OUTDIV2[1] Output divider2 control bit 1 R/W 0 Bit 3 OUTDIV2[0] Output divider2 control bit 0 R/W 1 Bit 2 OUT3_OUT_TRI OUT3 State Select R/W normal Tristate 0 Bit 1 OUT2_OUT_TRI OUT2 State Select R/W normal Tristate 0 Bit 0 OUT1_OUT_TRI OUT1 State Select R/W normal Tristate 0 Byte 10h Name Control Function Type 0 1 PWD Bit 7 OUT1_EN OUT1 output enable control R/W disable enable 1 Bit 6 OE1_fun_sel[1] OE1 pin function selection bit 1 R/W 11: DFC0 10: OUT1_PPS 01: PD# 00: OUT1 OE 0 Bit 5 OE1_fun_sel[0] OE1 pin function selection bit 0 R/W 0 Bit 4 OUT2_EN OUT2 output enable control R/W disable enable 1 Bit 3 OE2_fun_sel[1] OE2 pin function selection bit 1 R/W 11: DFC1 10: OUT2_PPS 01: Config_SEL 00: OUT2 OE 0 Bit 2 OE2_fun_sel[0] OE2 pin function selection bit 0 R/W 0 Bit 1 OUT2 Freerun OUT2 Freerun enable control R/W Freerun normal 1 Bit 0 OUT1 Freerun OUT1 Freerun enable control R/W Freerun normal 0 Byte 11h Name Control Function Type 0 1 PWD Bit 7 OUT1 CLKSEL 1 OUT1 output clock selection R/W 00: CLK32K, 01: OUTDIV2 10: NA, 11: OUTDIV1 0 Bit 6 OUT1 CLKSEL 0 OUT1 output clock selection R/W 0 Bit 5 OUT2 CLKSEL 1 OUT2 output clock selection R/W 00: CLK32K, 01: OUTDIV2 10: NA, 11: OUTDIV1 1 Bit 4 OUT2 CLKSEL 0 OUT2 output clock selection R/W 1 Bit 3 OUT3 CLKSEL 1 OUT3 output clock selection R/W 00: CLK32K, 01: OUTDIV2 10: REF, 11: OUTDIV1 1 Bit 2 OUT3 CLKSEL 0 OUT3 output clock selection R/W 0 Bit 1 OUT3_EN OUT3 output enable control R/W disable enable 1 Bit 0 DFC_EN DFC function control R/W disable enable 0 |
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