LTC2439-1IGN datasheet(8/28 Pages) LINER

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LTC2439-1

24391f

Once CS is pulled LOW, the device exits the low power

mode and enters the data output state. If CS is pulled HIGH

before the first rising edge of SCK, the device returns to the

low power sleep mode and the conversion result is still

held in the internal static shift register. If CS remains LOW

after the first rising edge of SCK, the device begins

outputting the conversion result and inputting channel

selection bits. Taking CS high at this point will terminate

the data output state and start a new conversion. The

channel selection control bits are shifted in through SDI

from the first rising edge of SCK and depending on the

control bits, the converter updates its channel selection

immediately and is valid for the next conversion. The

details of channel selection control bits are described in

the Input Data Mode section. The output data is shifted out

the SDO pin under the control of the serial clock (SCK). The

output data is updated on the falling edge of SCK allowing

APPLICATIO S I FOR ATIO

SDO

Hi-Z

SIG

(0)

BIT16

MSB

B22

CONVERSON RESULT

BIT15

BIT14

BIT13

BIT12

BIT11

BIT6

BIT5

BIT3

BIT2

BIT1

LSB

BIT0

BIT4

BIT17

SCK

SDI

SLEEP

DATA INPUT/OUTPUT

BIT18

EOC

(1)

(0)

SGL

DON’T CARE

CONVERSION

24391 F03a

ODD/

SIGN

CONVERSION RESULT

N – 1

ADDRESS

N + 1

ADDRESS

N + 2

OUTPUT

N – 1

OUTPUT

N + 1

SDO

SCK

SDI

OPERATION

Hi-Z

DON’T CARE

CONVERSION N

24391 F03b

CONVERSION N + 1

DON’T CARE

Hi-Z

CONVERSION RESULT

N + 1

Figure 3b. Typical Operation Sequence

the user to reliably latch data on the rising edge of SCK (see

Figure 3). The data output state is concluded once 19 bits

are read out of the ADC or when CS is brought HIGH. The

device automatically initiates a new conversion and the

cycle repeats. In order to maintain compatibility with

24-/32-bit data transfers, it is possible to clock the

LTC2439-1 with additional serial clock pulses. This results

in additional data bits which are always logic HIGH.

Through timing control of the CS and SCK pins, the

LTC2439-1 offers several flexible modes of operation

(internal or external SCK and free-running conversion

modes). These various modes do not require program-

ming configuration registers; moreover, they do not dis-

turb the cyclic operation described above. These modes of

operation are described in detail in the Serial Interface

Timing Modes section.

Figure 3a. Input/Output Data Timing

LTC2439-1IGN Datasheet(PDF) 8 Page - Linear Technology

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