LTC2439-1IGN datasheet(11/28 Pages) LINER

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LTC2439-1

24391f

Input Data Format

When the LTC2439-1 is powered up, the default selection

used for the first conversion is IN+ = CH0 and IN– = CH1

(Address = 00000). In the data input/output mode follow-

ing the first conversion, a channel selection can be up-

dated using an 8-bit word. The LTC2439-1 serial input data

is clocked into the SDI pin on the rising edge of SCK (see

Figure 3a). The input is composed of an 8-bit word with the

first 3 bits acting as control bits and the remaining 5 bits

as the channel address bits.

The first 2 bits are always 10 for proper updating opera-

tion. The third bit is EN. For EN = 1, the following 5 bits are

used to update the input channel selection. For EN = 0,

previous channel selection is kept and the following bits

are ignored. Therefore, the address is updated when the 3

control bits are 101 and kept for 100. Alternatively, the 3

control bits can be all zero to keep the previous address.

This alternation is intended to simplify the SDI interface

allowing the user to simply connect SDI to ground if no

update is needed. Combinations other than 101, 100 and

000 of the 3 control bits should be avoided.

When update operation is set (101), the following 5 bits

are the channel address. The first bit, SGL, decides if the

differential selection mode (SGL = 0) or the single-ended

selection mode is used (SGL = 1). For SGL = 0, two

adjacent channels can be selected to form a differential

input; for SGL = 1, one of the 16 channels (CH0-CH15) is

selected as the positive input and the COM pin is used as

the negative input. For a given channel selection, the

converter will measure the voltage between the two chan-

nels indicated by IN+ and IN– in the selected row of Table 1.

Output Data Format

The LTC2439-1 serial output data stream is 19 bits long.

The first 3 bits represent status information indicating the

conversion state and sign. The next 16 bits are the conver-

sion result, MSB first. The third and fourth bit together are

also used to indicate an underrange condition (both bits low

means the differential input voltage is below –FS) or an

overrange condition (both bits high means the differential

input voltage is above +FS).

Bit 18 (first output bit) is the end of conversion (EOC)

indicator. This bit is available at the SDO pin during the

conversion and sleep states whenever the CS pin is LOW.

This bit is HIGH during the conversion and goes LOW

when the conversion is complete.

Bit 17 (second output bit) is a dummy bit (DMY) and is

always LOW.

Bit 16 (third output bit) is the conversion result sign indi-

cator (SIG). If VIN is >0, this bit is HIGH. If VIN is <0, this

bit is LOW.

Bit 15 (fourth output bit) is the most significant bit (MSB)

of the result. This bit in conjunction with Bit 16 also

provides the underrange or overrange indication. If both

Bit 16 and Bit 15 are HIGH, the differential input voltage is

above +FS. If both Bit 16 and Bit 15 are LOW, the

differential input voltage is below –FS.

The function of these bits is summarized in Table 2.

Table 2. LTC2439-1 Status Bits

Bit 18

Bit 17

Bit 16

Bit 15

Input Range

EOC

DMY

SIG

MSB

VIN ≥ 0.5 • VREF

≤ VIN < 0.5 • VREF

–0.5 • VREF ≤ VIN < 0V

VIN < – 0.5 • VREF

Bits 15-0 are the 16-Bit conversion result MSB first.

Bit 0 is the least significant bit (LSB).

Data is shifted out of the SDO pin under control of the serial

clock (SCK), see Figure 3a. Whenever CS is HIGH, SDO

remains high impedance and any externally generated

SCK clock pulses are ignored by the internal data out shift

In order to shift the conversion result out of the device, CS

must first be driven LOW. EOC is seen at the SDO pin of the

device once CS is pulled LOW. EOC changes real time from

HIGH to LOW at the completion of a conversion. This

signal may be used as an interrupt for an external micro-

controller. Bit 18 (EOC) can be captured on the first rising

edge of SCK. Bit 17 is shifted out of the device on the first

falling edge of SCK. The final data bit (Bit 0) is shifted out

on the falling edge of the 18th SCK and may be latched on

the rising edge of the 19th SCK pulse. On the falling edge

of the 19th SCK pulse, SDO goes HIGH indicating the

initiation of a new conversion cycle. This bit serves as EOC

APPLICATIO S I FOR ATIO

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