Electronic Components Datasheet Search
  British  ▼
ALLDATASHEET.CO.UK

X  

USB334X Datasheet(PDF) 69 Page - Microchip Technology

Part # USB334X
Description  Enhanced Single Supply Hi-Speed USB ULPI Transceiver
PDF  92 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  MICROCHIP [Microchip Technology]
Direct Link  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

USB334X Datasheet(HTML) 69 Page - Microchip Technology

Back Button USB334X Datasheet HTML 65Page - Microchip Technology USB334X Datasheet HTML 66Page - Microchip Technology USB334X Datasheet HTML 67Page - Microchip Technology USB334X Datasheet HTML 68Page - Microchip Technology USB334X Datasheet HTML 69Page - Microchip Technology USB334X Datasheet HTML 70Page - Microchip Technology USB334X Datasheet HTML 71Page - Microchip Technology USB334X Datasheet HTML 72Page - Microchip Technology USB334X Datasheet HTML 73Page - Microchip Technology Next Button
Zoom Inzoom in Zoom Outzoom out
 69 / 92 page
background image
2009-2018 Microchip Technology Inc.
DS00002646A-page 69
USB334x
7.1.1.11
USB Interrupt Latch
Address = 14h (read only with auto clear)
Note 7-2
rd: Read Only with auto clear.
7.1.1.12
Debug
Address = 15h (read only)
7.1.1.13
Scratch Register
Address = 16-18h (read), 16h (write), 17h (set), 18h (clear)
Field Name
Bit
Access
Default
Description
HostDisconnect Latch
0
rd
(Note 7-2)
0b
Set to 1b by the PHY when an unmasked event
occurs on Hostdisconnect. Cleared when this register
is read. Applicable only in host mode.
VbusValid Latch
1
0b
Set to 1b by the PHY when an unmasked event
occurs on VbusValid. Cleared when this register is
read.
SessValid Latch
2
0b
Set to 1b by the PHY when an unmasked event
occurs on SessValid. Cleared when this register is
read.
SessEnd Latch
3
0b
Set to 1b by the PHY when an unmasked event
occurs on SessEnd. Cleared when this register is
read.
IdGnd Latch
4
0b
Set to 1b by the PHY when an unmasked event
occurs on IdGnd. Cleared when this register is read.
Reserved
7:5
rd
0h
Read only, 0.
Field Name
Bit
Access
Default
Description
Linestate[1:0]
1:0
rd
00b
Contains the current value of Linestate[1:0].
Reserved
7:2
rd
000000b
Read only, 0.
Field Name
Bit
Access
Default
Description
Scratch
7:0
rd/w/s/c
00h
Empty register byte for testing purposes. Software
can read, write, set, and clear this register and the
PHY functionality will not be affected.



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com