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AGLP030 Datasheet(PDF) 63 Page - Actel Corporation |
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AGLP030 Datasheet(HTML) 63 Page - Actel Corporation |
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63 / 128 page  IGLOO PLUS Low Power Flash FPGAs Re vi s i on 11 2 - 49 Output Enable Register Timing Characteristics 1.5 V DC Core Voltage Figure 2-16 • Output Enable Register Timing Diagram 50% Preset Clear EOUT CLK D_Enable 50% tOESUDtOEHD 50% 50% tOECLKQ 1 0 tOERECPRE tOEREMPRE tOERECCLR tOEREMCLR tOEWCLR tOEWPRE tOEPRE2Q tOECLR2Q tOECKMPWH tOECKMPWL 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% Table 2-78 • Output Enable Register Propagation Delays Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V Parameter Description Std. Units tOECLKQ Clock-to-Q of the Output Enable Register 0.68 ns tOESUD Data Setup Time for the Output Enable Register 0.33 ns tOEHD Data Hold Time for the Output Enable Register 0.00 ns tOECLR2Q Asynchronous Clear-to-Q of the Output Enable Register 0.84 ns tOEPRE2Q Asynchronous Preset-to-Q of the Output Enable Register 0.91 ns tOEREMCLR Asynchronous Clear Removal Time for the Output Enable Register 0.00 ns tOERECCLR Asynchronous Clear Recovery Time for the Output Enable Register 0.24 ns tOEREMPRE Asynchronous Preset Removal Time for the Output Enable Register 0.00 ns tOERECPRE Asynchronous Preset Recovery Time for the Output Enable Register 0.24 ns tOEWCLR Asynchronous Clear Minimum Pulse Width for the Output Enable Register 0.19 ns tOEWPRE Asynchronous Preset Minimum Pulse Width for the Output Enable Register 0.19 ns tOECKMPWH Clock Minimum Pulse Width High for the Output Enable Register 0.31 ns tOECKMPWL Clock Minimum Pulse Width Low for the Output Enable Register 0.28 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. |
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