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AGLP030 Datasheet(PDF) 64 Page - Actel Corporation

Part # AGLP030
Description  IGLOO PLUS Low Power Flash FPGAs with Flash*Freeze Technology
PDF  128 Pages
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Manufacturer  ACTEL [Actel Corporation]
Direct Link  http://www.actel.com
Logo ACTEL - Actel Corporation

AGLP030 Datasheet(HTML) 64 Page - Actel Corporation

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IGLOO PLUS DC and Switching Characteristics
2- 50
R e v i sio n 1 1
1.2 V DC Core Voltage
Table 2-79 • Output Enable Register Propagation Delays
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V
Parameter
Description
Std.
Units
tOECLKQ
Clock-to-Q of the Output Enable Register
1.06
ns
tOESUD
Data Setup Time for the Output Enable Register
0.52
ns
tOEHD
Data Hold Time for the Output Enable Register
0.00
ns
tOECLR2Q
Asynchronous Clear-to-Q of the Output Enable Register
1.25
ns
tOEPRE2Q
Asynchronous Preset-to-Q of the Output Enable Register
1.36
ns
tOEREMCLR
Asynchronous Clear Removal Time for the Output Enable Register
0.00
ns
tOERECCLR
Asynchronous Clear Recovery Time for the Output Enable Register
0.24
ns
tOEREMPRE
Asynchronous Preset Removal Time for the Output Enable Register
0.00
ns
tOERECPRE
Asynchronous Preset Recovery Time for the Output Enable Register
0.24
ns
tOEWCLR
Asynchronous Clear Minimum Pulse Width for the Output Enable Register
0.19
ns
tOEWPRE
Asynchronous Preset Minimum Pulse Width for the Output Enable Register
0.19
ns
tOECKMPWH
Clock Minimum Pulse Width High for the Output Enable Register
0.31
ns
tOECKMPWL
Clock Minimum Pulse Width Low for the Output Enable Register
0.28
ns
Note:
For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values.



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