AGLP030 datasheet(33/128 Pages) ACTEL

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IGLOO PLUS Low Power Flash FPGAs

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Overview of I/O Performance

Summary of I/O DC Input and Output Levels – Default I/O Software

Settings

Table 2-21 • Summary of Maximum and Minimum DC Input and Output Levels Applicable to Commercial and

Industrial Conditions—Software Default Settings

I/O Standard

Drive

Strength

Equiv.

Software

Default

Drive

Strength

Option2

Slew

Rate

VIL

VIH

VOL

VOH

IOL

1 I

Min.

Max.

Min.

Max.

Min.

VmA mA

3.3 V LVTTL /

3.3 V LVCMOS

12 mA

High –0.3

0.8

3.6

0.4

2.4

3.3 V LVCMOS

Wide Range3

100 µA

12 mA

High –0.3

0.8

3.6

0.2

VDD 3 0.2

0.1 0.1

2.5 V LVCMOS

12 mA

High –0.3

0.7

1.7

3.6

0.7

1.7

1.8 V LVCMOS

8 mA

High –0.3 0.35 * VCCI 0.65 * VCCI

3.6

0.45

VCCI – 0.45

1.5 V LVCMOS

4 mA

High –0.3 0.35 * VCCI 0.65 * VCCI

3.6

0.25 * VCCI 0.75 * VCCI

1.2 V

LVCMOS4

2 mA

High –0.3 0.35 * VCCI 0.65 * VCCI

3.6

0.25 * VCCI 0.75 * VCCI

1.2 V LVCMOS

Wide Range4,5

100 µA

2 mA

High –0.3 0.3 * VCCI

0.7 * VCCI

3.6

0.1

VCCI – 0.1

0.1 0.1

Notes:

1. Currents are measured at 85°C junction temperature.

2. Note that 1.2 V LVCMOS and 3.3 V LVCMOS wide range are applicable to 100 µA drive strength only. The configuration

will not operate at the equivalent software default drive strength. These values are for normal ranges only.

3. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD-8B specification.

4. Applicable to IGLOO PLUS V2 devices operating at VCCI ≥ VCC.

5. All LVCMOS 1.2 V software macros support LVCMOS 1.2 V wide range as specified in the JESD8-12 specification.

AGLP030 Datasheet(PDF) 33 Page - Actel Corporation

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