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LTC4230

4230f

INTERNAL UNDERVOLTAGE LOCKOUT (UVLO)

The LTC4230’s power-on reset circuit initializes the start-

up condition and ensures the chip is in the proper state if

the input supply voltages are too low. If any one of the

input supply voltages falls below its corresponding UVLO

lower threshold (e.g., VCC1 < 2.25V, VCC2 < 2.105V or VCC3

< 1.155V), the LTC4230 enters UVLO mode and all three

GATE

n pins are each pulled low by internal 200

µA current

sinks. Since the LTC4230’s UVLO circuits have hysteresis,

the device restarts when all three supply voltages rise

above their corresponding UVLO high threshold (e.g.,

VCC1 > 2.35V, VCC2 > 2.15V and VCC3 > 1.19V) and the ON

pin goes high.

In addition, users can utilize the ON comparator (COMP1)

or the FAULT comparator (COMP6) to effectively program

a higher undervoltage lockout level. If the FAULT com-

parator is used for this purpose, the system will wait for

the input voltage to increase above the level set by the user

before starting the second timing cycle. Also, if the input

voltage drops below the set level in normal operating

mode, the user must cycle the ON pin or VCC1 to restart the

system.

GLITCH FILTER FOR RESET

Each LTC4230 feedback comparator has a glitch filter to

prevent RESET

n from generating a system reset if there

are transients on the FB

n pin. The relationship between

glitch filter time and the feedback transient voltage is

shown in Figure 3.

SYSTEM TIMING

System timing for the LTC4230 is generated in the equiva-

lent circuit shown in Figure 4. If the LTC4230’s internal

timing circuit is off, an internal N-channel FET connects

the TIMER pin to GND. If the timing circuit is enabled, an

internal 20

µA current source is then connected to the

TIMER pin to charge CTIMER at a rate given by Equation 1:

Charge -Up Rate

TIMER

20 A

C TIMER

(1)

When the TIMER pin voltage reaches TMRHI’s threshold

of 1.234V, the TIMER pin is reset to GND. Equation 2 gives

an expression for the timer period:

TIMER

1 234

.•

(2)

As a design aid, the LTC4230’s timer period as a function

of the CTIMER using standard values from 0.1µF to 10µF is

shown in Table 1.

FEEDBACK TRANSIENT (mV)

150

200

250

160

4211 F03

100

120

180

100

140

200

TA = 25°C

Figure 3. FB Comparator Glitch Filter Time

vs Feedback Transient Voltage

–

0.3V

µA

tTIMER

LTC4230*

VCC1

VREF

1.234V

TMRLO

LOGIC

TMRHI

TIMER

CTIMER

NORMAL

4230 F04

*ADDITIONAL DETAILS OMITTED FOR CLARITY

Figure 4. LTC4230 System Timing Block Diagram

APPLICATIO S I FOR ATIO

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